Article

Evolving effective CA/CSTP: BIST architectures for sequential circuits

Authors:

F. Corno,

M. Sonza Reorda,

G. SquilleroAuthors Info & Claims

SAC '01: Proceedings of the 2001 ACM symposium on Applied computing

Pages 345 - 350

https://doi.org/10.1145/372202.372361

Published: 01 March 2001 Publication History

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F. Corno, M. Sonza Reorda, G. Squillero, "Evolving Cellular Automata for Self-Testing Hardware," ICES2000: Third International Conference on Evolvable Systems: From Biology to Hardware, Edinburgh (UK), April 2000, pp. 31-39]]

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F. Corno, M. Rebaudengo, M. Sonza Reorda, G. Squillero, M. Violante, "Low Power BIST via Hybrid Cellular Automata," VTS2000: 18th IEEE VLSI Test Symposium, Montreal, Canada (USA), May 2000, pp. 29-34]]

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F. Corno, M. Sonza Reorda, G. Squillero, "Exploiting the Selfish Gene Algorithm for Evolving Hardware Cellular Automata," CEC2000: Congress on Evolutionary Computation, San Diego (USA), July 2000, pp. 1401-1406]]

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A. Krasniewski, S. Pilarski, "Circular Self-Test Path: a Low-cost BIST Technique for VLSI Circuits," IEEE Trans. on Computer-Aided Design, Vol. 8, No. 1, Jan. 1989, pp. 46-55]]

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N.A. Touba, "Obtaining High Fault Coverage with Circular BIST via State Skipping," IEEE VLSI Test Symposium, 1997]]

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These benchmark circuits can be downloaded from the CAD Benchmarking Laborarory at the address http://www.cbl.ncsu.edu/www/CBL_Docs/Ben ch.html]]

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Cited By

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Khalid NAriff NFadzil ANoor N(2015)Selfish Gene Image Segmentation AlgorithmSoft Computing in Data Science10.1007/978-981-287-936-3_12(119-128)Online publication date: 12-Nov-2015
https://doi.org/10.1007/978-981-287-936-3_12
Al-Rabadi A(2008)Modeling and Processing Using Reversible Conservative Noisy Elementary Cellular Automata Circuits and their M-Ary Quantum ComputingIntelligent Automation & Soft Computing10.1080/10798587.2008.1064299014:2(177-206)Online publication date: Jan-2008
https://doi.org/10.1080/10798587.2008.10642990
Villagra ADe San Pedro MLasso MPandolfi D(2004)Multirecombined Evolutionary Algorithm Inspired in the Selfish Gene Theory to Face the Weighted Tardiness Scheduling ProblemAdvances in Artificial Intelligence – IBERAMIA 200410.1007/978-3-540-30498-2_81(809-819)Online publication date: 2004
https://doi.org/10.1007/978-3-540-30498-2_81
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Index Terms

Evolving effective CA/CSTP: BIST architectures for sequential circuits
1. Hardware
  1. Integrated circuits
    1. Logic circuits
      1. Sequential circuits
  2. Robustness

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ETW '00: Proceedings of the IEEE European Test Workshop

Circular Self-Test Path (CSTP) is an attractive technique for implementing BIST in sequential circuits; unfortunately, there are cases in which the fault coverage it attains is unacceptably low. This paper proposes a new architecture, named CA-CSTP, ...
An effective two-pattern test generator for Arithmetic BIST

Built-In Self Test (BIST) techniques perform test pattern generation and response verification operations on-chip. In Arithmetic BIST, modules that commonly exist in datapaths (accumulators, counters, etc.) are utilized to perform the above-mentioned ...
CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder
ASYNC '00: Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems

This paper presents a case study in low-cost non-invasive Built-In Self Test (BIST) for RAPPID, a large-scale 120,000-transistor asynchronous version of the Pentium Pro Instruction Length Decoder, which runs at 3.6 GHz. RAPPID uses a synchronous 0.25 ...

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SAC '01: Proceedings of the 2001 ACM symposium on Applied computing

March 2001

692 pages

ISBN:1581132875

DOI:10.1145/372202

Chairman:
G. B. Lamont
Air Force Institute of Technology

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Khalid NAriff NFadzil ANoor N(2015)Selfish Gene Image Segmentation AlgorithmSoft Computing in Data Science10.1007/978-981-287-936-3_12(119-128)Online publication date: 12-Nov-2015
https://doi.org/10.1007/978-981-287-936-3_12
Al-Rabadi A(2008)Modeling and Processing Using Reversible Conservative Noisy Elementary Cellular Automata Circuits and their M-Ary Quantum ComputingIntelligent Automation & Soft Computing10.1080/10798587.2008.1064299014:2(177-206)Online publication date: Jan-2008
https://doi.org/10.1080/10798587.2008.10642990
Villagra ADe San Pedro MLasso MPandolfi D(2004)Multirecombined Evolutionary Algorithm Inspired in the Selfish Gene Theory to Face the Weighted Tardiness Scheduling ProblemAdvances in Artificial Intelligence – IBERAMIA 200410.1007/978-3-540-30498-2_81(809-819)Online publication date: 2004
https://doi.org/10.1007/978-3-540-30498-2_81
Corno FReorda MSquillero G(2003)Built-In Self Test of Sequential CircuitsEvolutionary Algorithms for Embedded System Design10.1007/978-1-4615-1035-2_5(143-173)Online publication date: 2003
https://doi.org/10.1007/978-1-4615-1035-2_5

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CA-CSTP: A New BIST Architecture for Sequential Circuits

An effective two-pattern test generator for Arithmetic BIST

CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder

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