Article

Energy estimation and optimization of embedded VLIW processors based on instruction clustering

Authors:

R. ZafalonAuthors Info & Claims

DAC '02: Proceedings of the 39th annual Design Automation Conference

Pages 886 - 891

https://doi.org/10.1145/513918.514137

Published: 10 June 2002 Publication History

Abstract

Aim of this paper is to propose a methodology for the definition of an instruction-level energy estimation framework for VLIW (Very Long Instruction Word) processors. The power modeling methodology is the key issue to define an effective energy-aware software optimisation strategy for state-of-the-art ILP (Instruction Level Parallelism) processors. The methodology is based on an energy model for VLIW processors that exploits instruction clustering to achieve an efficient and fine grained energy estimation. The approach aims at reducing the complexity of the characterization problem for VLIW processors from exponential, with respect to the number of parallel operations in the same very long instruction, to quadratic, with respect to the number of instruction clusters. Furthermore, the paper proposes a spatial scheduling algorithm based on a low-power reordering of the parallel operations within the same long instruction. Experimental results have been carried out on the Lx processor, a 4-issue VLIW core jointly designed by HPLabs and STMicroelectronics. The results have shown an average error of 1.9% between the cluster-based estimation model and the reference design, with a standard deviation of 5.8%. For the Lx architecture, the spatial instruction scheduling algorithm provides an average energy saving of 12%.

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Cited By

Diop TJerger NAnderson JCavazos JGong XKaeli D(2014)Power Modeling for Heterogeneous ProcessorsProceedings of Workshop on General Purpose Processing Using GPUs10.1145/2588768.2576790(90-98)Online publication date: 1-Mar-2014
https://dl.acm.org/doi/10.1145/2588768.2576790
Kobayashi YJayapala MRaghavan PCatthoor FImai M(2007)Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processorsACM Transactions on Design Automation of Electronic Systems10.1145/1278349.127835412:4(41-es)Online publication date: 1-Sep-2007
https://dl.acm.org/doi/10.1145/1278349.1278354
Xiao SLai E(2007)VLIW instruction scheduling for minimal power variationACM Transactions on Architecture and Code Optimization10.1145/1275937.12759424:3(18-es)Online publication date: 1-Sep-2007
https://dl.acm.org/doi/10.1145/1275937.1275942
Show More Cited By

Index Terms

Energy estimation and optimization of embedded VLIW processors based on instruction clustering
1. Hardware
  1. Integrated circuits
    1. Logic circuits

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cover image ACM Conferences

DAC '02: Proceedings of the 39th annual Design Automation Conference

June 2002

956 pages

ISBN:1581134614

DOI:10.1145/513918

General Chair:
Bryan Ackland
Agere Systems, Inc., Holmdel, NJ

Copyright © 2002 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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New York, NY, United States

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Published: 10 June 2002

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DAC02: 39th Design Automation Conference

June 10 - 14, 2002

Louisiana, New Orleans, USA

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DAC '02 Paper Acceptance Rate 147 of 491 submissions, 30%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Diop TJerger NAnderson JCavazos JGong XKaeli D(2014)Power Modeling for Heterogeneous ProcessorsProceedings of Workshop on General Purpose Processing Using GPUs10.1145/2588768.2576790(90-98)Online publication date: 1-Mar-2014
https://dl.acm.org/doi/10.1145/2588768.2576790
Kobayashi YJayapala MRaghavan PCatthoor FImai M(2007)Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processorsACM Transactions on Design Automation of Electronic Systems10.1145/1278349.127835412:4(41-es)Online publication date: 1-Sep-2007
https://dl.acm.org/doi/10.1145/1278349.1278354
Xiao SLai E(2007)VLIW instruction scheduling for minimal power variationACM Transactions on Architecture and Code Optimization10.1145/1275937.12759424:3(18-es)Online publication date: 1-Sep-2007
https://dl.acm.org/doi/10.1145/1275937.1275942
Junior MNeto SMaciel PLima RRibeiro ABarreto RTavares EBraga F(2006)Analyzing software performance and energy consumption of embedded systems by probabilistic modelingProceedings of the 27th international conference on Applications and Theory of Petri Nets and Other Models of Concurrency10.1007/11767589_15(261-281)Online publication date: 26-Jun-2006
https://dl.acm.org/doi/10.1007/11767589_15
Xiao SLai EPremkumar A(2005)Rule-Based power-balanced VLIW instruction scheduling with uncertaintyProceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture10.5555/2162778.2162784(28-40)Online publication date: 24-Oct-2005
https://dl.acm.org/doi/10.5555/2162778.2162784
Monchiero MPalermo GSami MSilvano CZaccaria VZafalon R(2005)Low-power branch prediction techniques for VLIW architecturesIntegration, the VLSI Journal10.5555/1062115.106212738:3(515-524)Online publication date: 1-Jan-2005
https://dl.acm.org/doi/10.5555/1062115.1062127
Senn ELaurent JJulien NMartin E(2005)SoftexplorerEURASIP Journal on Advances in Signal Processing10.1155/ASP.2005.26412005(2641-2654)Online publication date: 1-Jan-2005
https://dl.acm.org/doi/10.1155/ASP.2005.2641
Xiao SLai ETang T(2005)Instruction scheduling of VLIW architectures for balanced power consumptionProceedings of the 2005 Asia and South Pacific Design Automation Conference10.1145/1120725.1121027(824-829)Online publication date: 18-Jan-2005
https://dl.acm.org/doi/10.1145/1120725.1121027
Meyer BPieper JPaul JNelson JPieper SRowe A(2005)Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous MultiprocessorsIEEE Transactions on Computers10.1109/TC.2005.10354:6(684-697)Online publication date: 1-Jun-2005
https://dl.acm.org/doi/10.1109/TC.2005.103
Monchiero MPalermo GSami MSilvano CZaccaria VZafalon R(2005)Low-power branch prediction techniques for VLIW architecturesIntegration, the VLSI Journal10.1016/j.vlsi.2004.07.01238:3(515-524)Online publication date: 1-Jan-2005
https://dl.acm.org/doi/10.1016/j.vlsi.2004.07.012
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