Computer Science > Distributed, Parallel, and Cluster Computing
[Submitted on 28 May 2019 (v1), last revised 11 Sep 2020 (this version, v2)]
Title:Energy Efficiency Features of the Intel Skylake-SP Processor and Their Impact on Performance
View PDFAbstract:The overwhelming majority of High Performance Computing (HPC) systems and server infrastructure uses Intel x86 processors. This makes an architectural analysis of these processors relevant for a wide audience of administrators and performance engineers. In this paper, we describe the effects of hardware controlled energy efficiency features for the Intel Skylake-SP processor. Due to the prolonged micro-architecture cycles, which extend the previous Tick-Tock scheme by Intel, our findings will also be relevant for succeeding architectures. The findings of this paper include the following: C-state latencies increased significantly over the Haswell-EP processor generation. The mechanism that controls the uncore frequency has a latency of approximately 10 ms and it is not possible to truly fix the uncore frequency to a specific level. The out-of-order throttling for workloads using 512 bit wide vectors also occurs at low processor frequencies. Data has a significant impact on processor power consumption which causes a large error in energy models relying only on instructions.
Submission history
From: Robert Schöne [view email][v1] Tue, 28 May 2019 12:08:50 UTC (385 KB)
[v2] Fri, 11 Sep 2020 08:40:54 UTC (385 KB)
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