research-article

A soft error vulnerability analysis framework for Xilinx FPGAs

Authors:

Dimitris Agiakatsikas,

Mihalis PsarakisAuthors Info & Claims

FPGA '14: Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays

Pages 237 - 240

https://doi.org/10.1145/2554688.2554767

Published: 26 February 2014 Publication History

Abstract

Today's SRAM-based FPGAs provide a reach set of computing resources which makes them attractive in demanding and critical application domains, such as avionics and space. Unfortunately, their high reliance on SRAM configuration memory arise reliability issues due to the single-event upsets (SEUs). Considering the criticality of these applications, the vulnerability analysis of FPGA designs to SEUs becomes essential part of the design flow. In this context, we present an open-source framework for the soft error vulnerability analysis of Xilinx FPGA devices. The proposed framework will allow researchers to evaluate their reliability-aware CAD algorithms and estimate the soft error susceptibility of the designs at early stages of the implementation flow for the latest Xilinx architectures.

References

[1]

Abdul-Aziz, M. A. and Tahoori, M. B., 2010. Soft error reliability aware placement and routing for FPGAs. In Test Conference (ITC), 2010 IEEE International, 1--9.

[2]

Altera, 2010. Benchmark Designs For The Quartus University Interface Program (QUIP) Version 1.1, https://www.altera.com/support/software/download/altera_design/quip/quip-download.jsp.

[3]

Asadi, G. and Tahoori, M. B., 2005. Soft error rate estimation and mitigation for SRAM-based FPGAs. ACM/SIGDA 13th international symposium on Field-programmable gate arrays, ACM, 1046212, 149--160.

Digital Library

[4]

Betz, V., 2009. FPGA challenges and opportunities at 40nm and beyond. In Field Programmable Logic and Applications, 2009. International Conference on, 4--4.

[5]

Betz, V. and Rose, J., 1997. VPR: a new packing, placement and routing tool for FPGA research, 213--222.

Digital Library

[6]

Bolchini, C., Miele, A., and Sandionigi, C., 2011. A Novel Design Methodology for Implementing Reliability-Aware Systems on SRAM-Based FPGAs. Computers, IEEE Transactions on 60, 12, 1744--1758.

Digital Library

[7]

Hiemstra, D. M. and Kirischian, V., 2012. Single Event Upset Characterization of the Virtex-6 Field Programmable Gate Array Using Proton Irradiation. In Radiation Effects Data Workshop (REDW), 2012 IEEE, 1--4.

[8]

Hung, E., Eslami, F., and Wilton, S. J. E., 2013. Escaping the Academic Sandbox: Realizing VPR Circuits on Xilinx Devices. In Field-Programmable Custom Computing Machines (FCCM), 21st Annual Intern. Sympos. on, 45--52.

Digital Library

[9]

Lavin, C., Padilla, M., Lamprecht, J., Lundrigan, P., Nelson, B., and Hutchings, B., 2011. RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs. In Field Programmable Logic and Applications, 349--355.

Digital Library

[10]

Srinivasan, S., Krishnan, R., Mangalagiri, P., Yuan, X., Narayanan, V., Irwin, M. J., and Sarpatwari, K., 2008. Toward Increasing FPGA Lifetime. Dependable and Secure Computing, IEEE Transactions on 5, 2, 115--127.

Digital Library

[11]

Steiner, N., Wood, A., Shojaei, H., Couch, J., Athanas, P., and French, M., 2011. Torc: towards an open-source tool flow. 19th ACM/SIGDA international symposium on Field programmable gate arrays, ACM, 1950425, 41--44.

Digital Library

[12]

Sterpone, L. and Violante, M., 2007. A New Partial Reconfiguration-Based Fault-Injection System to Evaluate SEU Effects in SRAM-Based FPGAs. Nuclear Science, IEEE Transactions on 54, 4, 965--970.

[13]

Violante, M., Sterpone, L., Ceschia, M., Bortolato, D., Bernardi, P., Reorda, M. S., and Paccagnella, A., 2004. Simulation-based analysis of SEU effects in SRAM-based FPGAs. Nuclear Science, IEEE Trans. on 51, 6, 3354--3359.

[14]

Wirthlin, M., Johnson, E., Rollins, N., Caffrey, M., and Graham, P., 2003. The reliability of FPGA circuit designs in the presence of radiation induced configuration upsets. In Field-Programmable Custom Computing Machines, 2003. FCCM 2003. 11th Annual IEEE Symposium on, 133--142.

Digital Library

[15]

Zarandi, H. R., Miremadi, S. G., Pradhan, D. K., and Mathew, J., 2007. SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-Based FPGAs. In Quality Electronic Design, 2007. ISQED '07, 380--385.

Digital Library

Cited By

Agiakatsikas DFoutris NSari AVlagkoulis VSouvatzoglou IPsarakis MYe RGoodacre JLuján MKastriotou MCazzaniga CFrost C(2024)Single Event Effects Assessment of UltraScale+ MPSoC Systems Under Atmospheric RadiationIEEE Transactions on Reliability10.1109/TR.2023.331254873:1(771-783)Online publication date: Mar-2024
https://doi.org/10.1109/TR.2023.3312548
Bricas GTsiligiannis GBoch JBricas S(2024)A New Analytical Approach to Evaluate the Radiation Sensitivity of Circuits Implemented on SRAM-Based FPGAsIEEE Transactions on Nuclear Science10.1109/TNS.2024.346700971:10(2230-2241)Online publication date: Oct-2024
https://doi.org/10.1109/TNS.2024.3467009
Sari APsarakis M(2020)Scrubbing-Aware Placement for Reliable FPGA SystemsIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2017.27579788:3(564-576)Online publication date: 1-Jul-2020
https://doi.org/10.1109/TETC.2017.2757978
Show More Cited By

Index Terms

A soft error vulnerability analysis framework for Xilinx FPGAs
1. Hardware
  1. Hardware test
  2. Robustness

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Published In

cover image ACM Conferences

FPGA '14: Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays

February 2014

272 pages

ISBN:9781450326711

DOI:10.1145/2554688

General Chair:
Vaughn Betz
University of Toronto, Canada
,
Program Chair:
George A. Constantinides
Imperial College London, UK

Copyright © 2014 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 26 February 2014

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Research-article

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FPGA'14

Sponsor:

SIGDA

FPGA'14: The 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

February 26 - 28, 2014

California, Monterey, USA

Acceptance Rates

FPGA '14 Paper Acceptance Rate 30 of 110 submissions, 27%;

Overall Acceptance Rate 125 of 627 submissions, 20%

Upcoming Conference

FPGA '25

Sponsor:
sigda

The 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays

February 27 - March 1, 2025

Monterey , CA , USA

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Cited By

Agiakatsikas DFoutris NSari AVlagkoulis VSouvatzoglou IPsarakis MYe RGoodacre JLuján MKastriotou MCazzaniga CFrost C(2024)Single Event Effects Assessment of UltraScale+ MPSoC Systems Under Atmospheric RadiationIEEE Transactions on Reliability10.1109/TR.2023.331254873:1(771-783)Online publication date: Mar-2024
https://doi.org/10.1109/TR.2023.3312548
Bricas GTsiligiannis GBoch JBricas S(2024)A New Analytical Approach to Evaluate the Radiation Sensitivity of Circuits Implemented on SRAM-Based FPGAsIEEE Transactions on Nuclear Science10.1109/TNS.2024.346700971:10(2230-2241)Online publication date: Oct-2024
https://doi.org/10.1109/TNS.2024.3467009
Sari APsarakis M(2020)Scrubbing-Aware Placement for Reliable FPGA SystemsIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2017.27579788:3(564-576)Online publication date: 1-Jul-2020
https://doi.org/10.1109/TETC.2017.2757978
Sharma JRao NMohamed O(2020)Fault Injection Controller Based Framework to Characterize Multiple Bit Upsets for FPGA Designs2020 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)10.1109/IPFA49335.2020.9260845(1-5)Online publication date: 20-Jul-2020
https://doi.org/10.1109/IPFA49335.2020.9260845
Abid FJayasinghe DSomsavaddy SParameswaran S(2020)LFTSM: Lightweight and Fully Testable SEU Mitigation System for Xilinx Processor-Based SoCs2020 30th International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL50879.2020.00036(162-168)Online publication date: Aug-2020
https://doi.org/10.1109/FPL50879.2020.00036
Nelson B(2019)Third Party CAD Tools for FPGA Design—A Survey of the Current LandscapeIntelligent Information and Database Systems10.1007/978-3-030-17227-5_25(353-367)Online publication date: 29-Mar-2019
https://doi.org/10.1007/978-3-030-17227-5_25
Agiakatsikas DCetin EDiessel O(2018)FMER: An Energy-Efficient Error Recovery Methodology for SRAM-Based FPGA DesignsIEEE Transactions on Aerospace and Electronic Systems10.1109/TAES.2018.282820154:6(2695-2712)Online publication date: Dec-2018
https://doi.org/10.1109/TAES.2018.2828201
Lee GAgiakatsikas DWu TCetin EDiessel O(2017)TLegUp: A TMR Code Generation Tool for SRAM-Based FPGA Applications Using HLS2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM.2017.57(129-132)Online publication date: Apr-2017
https://doi.org/10.1109/FCCM.2017.57
Chadjiminas ISavva IKyrkou CMichael MTheocharides TFanucci LTeich J(2016)Emulation-based hierarchical fault-injection framework for coarse-to-fine vulnerability analysis of hardware-accelerated approximate algorithmsProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2971999(830-833)Online publication date: 14-Mar-2016
https://dl.acm.org/doi/10.5555/2971808.2971999
Sari APsarakis M(2016)A fault injection platform for the analysis of soft error effects in FPGA soft processors2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)10.1109/DDECS.2016.7482459(1-6)Online publication date: Apr-2016
https://doi.org/10.1109/DDECS.2016.7482459
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