A low cost hierarchical system for VLSI layout and verification
Abstract
With IC complexity and the manhour effort required for design doubling every two years, new approaches to layout and mask verification are required. A low-cost VLSI layout and verification system was developed to produce cost effective designs using present resources. The system is IC technology independent, makes effective use of present design skills while maintaining density, and includes structured and behavioral intelligence to aid design verification. In addition, it is easy to learn to use since it provides a simplified design methodology for layout.
References
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Index Terms
- A low cost hierarchical system for VLSI layout and verification
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Published In
June 1981
899 pages
Sponsors
- SIGDA: ACM Special Interest Group on Design Automation
- IEEE-CS\DATC: IEEE Computer Society
Publisher
IEEE Press
Publication History
Published: 29 June 1981
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