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A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing scheme

Authors:

Hiroaki Yamaoka,

Makoto Ikeda,

Kunihiro AsadaAuthors Info & Claims

ASP-DAC '01: Proceedings of the 2001 Asia and South Pacific Design Automation Conference

Pages 3 - 4

https://doi.org/10.1145/370155.370195

Published: 30 January 2001 Publication History

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Abstract

In this paper, a high-speed PLA based on latch sense amplifiers and a charge sharing scheme is resented. The circuit consists of logic cell arrays, dual-rail bit-lines, latch sense amplifiers, and control blocks. By latch sense amplifiers, a read-out scheme sensing the differential voltage of dual-rail bit-lines caused by charge sharing is used for high-speed operation. As an application of the proposed PLA, a 32-bit binary comparator is designed and implemented in a 0.6-um double-poly, triple-metal CMOS process. Results of HSPICE simulation are 2.9 times faster than the conventional CMOS circuit. The measured results show a good agreement with the simulation.

References

[1]

M.Matsui et al.,"A 200 MHz 13 mm 2 2-D DCT Macrocell Using Sense-Amplifying Pipeline Flip-Flop Scheme," IEEE J. Solid-State Circuits,vol.29,pp.1482-1490,Dec.1994.

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[2]

O.Takahashi,N.Aoki,J.Silberman,and S.Dhong,"1GHz Logic Circuits with Sense Ampli .ers," in Symp.VLSI Circuits Dig.Tech.Papers,1998,pp.110-111.

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Molavi RMirabbasi SSaleh R(2006)A High-Speed Low-Energy Dynamic PLA Using an Input-Isolation Scheme2006 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2006.1693227(2885-2888)Online publication date: 2006
https://doi.org/10.1109/ISCAS.2006.1693227
Yoshida HYamaoka HIkeda MAsada K(2002)Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLAProceedings of the 2002 Asia and South Pacific Design Automation Conference10.5555/832284.835468Online publication date: 7-Jan-2002
https://dl.acm.org/doi/10.5555/832284.835468

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A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing scheme

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ASP-DAC '01: Proceedings of the 2001 Asia and South Pacific Design Automation Conference

January 2001

662 pages

ISBN:0780366344

DOI:10.1145/370155

Chairman:
Satoshi Goto
NEC Corp., Kawasaki, Japan

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 30 January 2001

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ASP-DAC01: Asia and South Pacific Design Automation Conference 2001

Yokohama, Japan

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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Molavi RMirabbasi SSaleh R(2006)A High-Speed Low-Energy Dynamic PLA Using an Input-Isolation Scheme2006 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2006.1693227(2885-2888)Online publication date: 2006
https://doi.org/10.1109/ISCAS.2006.1693227
Yoshida HYamaoka HIkeda MAsada K(2002)Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLAProceedings of the 2002 Asia and South Pacific Design Automation Conference10.5555/832284.835468Online publication date: 7-Jan-2002
https://dl.acm.org/doi/10.5555/832284.835468

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An improved high speed, and low voltage CMOS current mode logic latch

Cellular Logic Array for High-Speed Signed Binary Number Multiplication

A Current-Mode Logic for Low-Voltage, High-Speed Mixed-Mode VLSI Circuits

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An improved high speed, and low voltage CMOS current mode logic latch

Cellular Logic Array for High-Speed Signed Binary Number Multiplication

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