A fast learning-driven signoff power optimization framework

Modern high-performance System-on-Chip (SoC) design flows highly depend on signoff tools to perform timing-constrained power optimization through Engineering Change Orders (ECOs), which involve gate-sizing and V_th-assignment of standard cells. However, ECOs are highly time-consuming, and the power improvement is unknown in advance. Ever since the industrial benchmarks released by the ISPD-2012 gate-sizing contest, active research has been conducted extensively. Nonetheless, previous works were mostly based on heuristics or analytical methods whose timing models were over-simplified and lacked formal validations from commercial signoff tools. In this paper, we propose ECO-GNN, a transferable graph-learning-based framework, which harnesses graph neural networks (GNNs) to perform commercial-quality signoff power optimization through discrete V_th-assignment. Our framework generates tool-accurate optimization results instantly on unseen netlists that are not utilized in the training process. Furthermore, we implement a GNN-based explanation method to interpret the optimization results achieved by our framework. Experimental results on 14 industrial designs, including a RISC-V-based multi-core system and the renowned ISPD-2012 benchmarks, demonstrate that our framework achieves up to 14X runtime improvement with similar signoff power optimization quality compared with Synopsys PrimeTime.