Regular Section
99.4% Switching Energy Saving and 87.5% Area Reduction Switching Scheme for SAR ADC
2015 Volume E98.C Issue 10 Pages 984-986
Details
2015 Volume E98.C Issue 10 Pages 984-986
A high energy-efficiency and area-reduction switching scheme for a low-power successive approximation register (SAR) analog-to-digital converter (ADC) is presented. Based on the sequence initialization, monotonic capacitor switching procedure and multiple reference voltages, the average switching energy and total capacitance of the proposed scheme are reduced by 99.4% and 87.5% respectively, compared to the conventional architecture.
