Yield learning and silicon debug have evolved in the era of high complexity SoCs and multi-die systems. Marc Hutner, Director, Product Management, Tessent explains how in this podcast with SemiWiki.com. Marc discusses improving Yield Insights through AI, ML and other techniques that can result in millions of dollars of savings. Listen to the full podcast to learn more. https://sie.ag/3XDYUr #YieldLearning #yieldmanagement #TessentYieldInsight #DFTmarketleader #Tessent #semiconductor #SiemensEDA
Tessent Silicon Lifecycle Solutions
Software Development
Wilsonville, Oregon 4,007 followers
Delivering transformative test, functional monitoring and security technology for SoC manufacturers
About us
Siemens EDA Tessent offers a suite of tools for design-for-test (DFT), design-for-diagnosis (DFD), and design-for-reliability (DFR) in semiconductor devices. These solutions improve testability, diagnosis, and reliability in electronic designs, contributing to the creation of high-quality, functional semiconductor devices. Tessent Silicon Lifecycle Solutions delivers design augmentation and linked applications that detect, mitigate and eliminate risks throughout the IC lifecycle, helping customers address their debug, test, yield, safety, security, and optimization requirements for today’s most complex SoCs. Tessent solutions fall into 2 main categories. Tessent Test and Embedded Analytics. TESSENT TEST: DFT and Operations Design for test and operations products for logic, memory and mixed-signal devices. The Tessent Test Solutions product suite provides comprehensive silicon test and operations applications and IP that addresses the challenges of manufacturing test, debug, and yield ramp for today’s most complex SoCs. TESSENT EMBEDDED ANALYTICS: On-Chip monitoring Tessent Embedded Analytics combines silicon IP and software to provide an intelligent functional monitoring and analytics infrastructure for SoCs. Our Embedded Analytics technology puts cybersecurity and functional safety features into the systems-on-chip (SoCs) at the heart of today’s electronic products. LEARN MORE Visit the Tessent website: www. https://eda.sw.siemens.com/en-US/ic/tessent/ Email: [email protected]
- Website
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https://eda.sw.siemens.com/en-US/ic/tessent/
External link for Tessent Silicon Lifecycle Solutions
- Industry
- Software Development
- Company size
- 5,001-10,000 employees
- Headquarters
- Wilsonville, Oregon
- Specialties
- DFT, Embedded Analytics, Tessent Multi-die, Tessent Streaming Scan Network, Tessent TestKompress, Tessent MemoryBIST, Tessent LogicBIST, Tessent IJTAG, Tessent DefectSim, Tessent FastScan, Tessent ScanPro, Tessent MissionMode, Tessent BoundaryScan, Tessent Diagnosis, Tessent YieldInsight, Tessent SiliconInsight, RISC-V Enhanced Trace Encoder, Tessent ESDK, and Tessent Embedded Software Development Kit
Updates
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Discover the AI design challenges faced with traditional tests by Habana Labs in this presentation by Sagie Fisher, DFT Manager. As well as explaining the design challenges, Sagie presents options to solve them and describes their flow switching from traditional DFT solutions to future solutions, as they cope with AI complexity and scale increase every generation. He also examines the development process from chip DFT architecture, implementation challenges, and silicon results and shows the benefits of moving to an advanced solution and the results seen on silicon. To learn more, watch the full presentation now: https://sie.ag/557T6i #designfortest #AIchips #DFTMarketleader #Tessent #Semiconductors #3DIC #SiemensEDA
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New webinar from Lauterbach GmbH and Siemens EDA, that explains how processor trace gives software developers access to critical insights and forensic capabilities, and how, by managing the risk of building embedded systems, it can be used to improve embedded software and applications. Don't miss this exclusive webinar to learn about: - What the RISC-V Efficient trace (E-trace) standard is & how it reduces some of the risks of adopting RISC-V. - How the non-intrusive visibility that it provides is used to understand program behavior for advanced debugging and code optimization. - How the Tessent Enhanced Trace Encoder is part of a complete SoC debug solution. - How to use Lauterbach’s TRACE32® Debug and Trace tools to gain extensive insight into a RISC-V SoC with Tessent Embedded Analytics. Learn more and register for one of the following live webinar sessions on Tues, 8 Oct . Europe | 11am CEST | https://sie.ag/7RzgH4 USA | 9am PDT | https://sie.ag/2kt1wm #RISCV #RISCVeverywhere #RISCVEfficientTrace #RISCVEtrace #TessentEmbeddedAnalytics #SiemensEDA
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If you are attending IP SoC China in Shanghai this week, 12th Sept, be sure to pop by Booth #15 and meet experts from Siemens EDA where you can gain an expert introduction to our range of industry leading RISC-V solutions that help manage the risk of adopting RISC-V. There is also a special technical presentation by Yifan Li, Account Technology Manager, in which he shares how Kalray Kalray optimize their complex software with Tessent Enhanced Trace Encoder. Kalray were looking to address trace and debug challenges of their complex software stack and leveraged the Enhanced Trace Encoder IP module from Tessent Embedded Analytics. Their use of embedded features, such as branch prediction and jump target cache, led to a significant compression ratio, resulting in optimized performances of the entire system. Learn more on Booth #15, we look forward to meeting you there. For more information & to register, visit. https://sie.ag/5bj8Xb #TessentEtrace #TessentEnhancedTraceEncoder #TessentEmbeddedAnalytics #RISCV #SiemensEDA
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Last call for the new, live Tessent webinar taking place tomorrow that will introduce the latest scan chain diagnosis improvements from Siemens EDA. Presented by Jayant D'Souza, Principal Technical Product Manager, Tessent, the webinar will introduce 3 new software-based technologies that provide accurate localization to enable efficient failure analysis of both front-end and back-end line defects. As well as sharing the results for each of these techniques, Jayant will also explain further technologies that can alleviate the pressure on fault isolation for front-end of line defects and provide reduced area for back-end of line defects for Physical Failure Analysis (PFA). With the advent of new technologies, like backside power in advanced process nodes, making fault isolation extremely challenging, don't miss this exclusive opportunity to learn how to address these issues. Register now and reserve your free webinar place. https://sie.ag/BAKvs #HiResChain #YieldLearning #Scanchaindiagnosis #chiplets #DFT #Tessent #DFTMarketLeader #SiemensEDA #3DIC #semiconductors
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With software defined vehicles driving advancements in Semiconductor design, gain an introduction to Siemens EDA wide range of technologies & software solutions that help address the challenges of delivering safe & secure Semiconductors to power future vehicles. Don’t miss this exclusive Automotive Technology Day, 24 Sept, at the Audi Conference Center in Munich, to learn more about Siemens EDA complete end to end solution for the automotive industry. The TechDay also includes a special Industry keynote by Laith Altimime, President, SEMI Europe. Learn more about the agenda and register for free today at. https://sie.ag/35LmhM #Automotivecybersecurity #Automotivesafety #TessentEmbeddedAnalytics #SecureCAV #Tessent #DFTMarketleader #semiconductors
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Tessent Silicon Lifecycle Solutions reposted this
The exponential growth in compute demands of AI, and the move to Software Defined Products, means that more than ever workloads are defining the semiconductor requirements. The need to hit the restrictive power, performance, area and cost constraints of edge designs, mean that every element of the design needs to be optimized and co-designed with the workloads in mind. Additionally, the design needs to evolve even after semiconductor design is complete as it adapts to new demands. In this presentation, Ankur Gupta, Senior Vice President and General Manager, Siemens EDA (Siemens Digital Industries Software), shares his insights on how semiconductor design is changing to enable rapid development and deployment of custom, application optimized, system-on-chip designs – from concept through to in-life operation, as we chart the path to a sustainable compute future. Join Ankur at the AI Hardware & Edge AI Summit, on September 10th at 11:15AM at Signia by Hilton, San Jose, CA. Use SIEMENSPLATINUM20 for 20% off your registration - link is in the comments! #EDA #AIHWEdgeAISummit #AI #EdgeAI #AIHardware #Semiconductor
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Don't miss the opportunity to meet experts from Siemens EDA next week at IP SoC China in Shanghai, 12th September, and to gain an expert introduction to our range of industry leading RISC-V solutions that help manage the risk of adopting RISC-V. Plus don't miss the special technical presentation by Yifan Li, Account Technology Manager, as he shares how Kalray optimize their complex software with Tessent Enhanced Trace Encoder. Kalray were looking to address trace and debug challenges of their complex software stack and leveraged the Enhanced Trace Encoder IP module from Tessent Embedded Analytics. Their use of embedded features, such as branch prediction and jump target cache, led to a significant compression ratio, resulting in optimized performances of the entire system. Learn more on Booth #15, we look forward to meeting you there. For more information & to register, visit. https://sie.ag/2p1R5T #TessentEtrace #TessentEnhancedTraceEncoder #TessentEmbeddedAnalytics #RISCV #SiemensEDA
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Don't miss next week's live Tessent webinar, presented by Jayant D'Souza, Principal Technical Product Manager, in which he introduces the latest scan chain diagnosis improvements from Siemens EDA. This informative webinar will detail three new software-based technologies that provide accurate localization to enable efficient failure analysis of both front-end and back-end line defects. As well as sharing the results for each of these techniques, Jayant will also introduce further technologies that can alleviate the pressure on fault isolation for front-end of line defects and provide reduced area for back-end of line defects for Physical Failure Analysis (PFA). With the advent of new technologies, like backside power in advanced process nodes, making fault isolation extremely challenging, don't miss this live webinar to learn how to address these issues. Learn more & reserve your free webinar place today. https://sie.ag/7U9fJ6 #HiResChain #YieldLearning #Scanchaindiagnosis #chiplets #DFT #Tessent #DFTMarketLeader #SiemensEDA #3DIC #semiconductors
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Tessent Silicon Lifecycle Solutions reposted this
Siemens Automotive Semiconductor Technology Day 24th September 2024 Munich Audi Conference Center (Munich Airport) Software Defined Vehicles are driving the innovation and advancements in Semiconductor technologies for the Automotive industry. Siemens EDA has a wide range of technologies to help to address the challenges of delivering safe and secure Semiconductor technologies to power these vehicles. To understand more about Siemens complete end to end solution Join us 24th September 2024 Audi Conference center (Munich Airport) REGISTER NOW TO SECURE YOUR PLACE https://lnkd.in/dH3mvnyq