Cited By
View all- Lyu LWang YChen CRichard Shi C(2020)A 0.6V 1.07 μW/Channel neural interface IC using level-shifted feedbackIntegration, the VLSI Journal10.1016/j.vlsi.2019.11.00170:C(51-59)Online publication date: 1-Jan-2020
A low-voltage low-power multi-channel neural interface IC using level-shifted feedback technology
Pages 13 - 14
Abstract
A low-voltage low-power 16-channel neural interface front-end IC for in-vivo neural recording applications is presented in this paper. A current reuse telescope amplifier is used to achieve better noise efficiency factor (NEF). Power efficiency factor (PEF) is further improved by reducing supply voltage with the proposed level-shifted feedback (LSFB) technique. The neural interface is fabricated in a 65 nm CMOS process. It operates under 0.6V supply voltage consuming 1.07 μW/channel. An input referred noise of 5.18 μV is measured, leading to a NEF of 2.94 and a PEF of 5.19 over 10 kHz bandwidth.
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- A low-voltage low-power multi-channel neural interface IC using level-shifted feedback technology
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- IEICE ESS: Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
- IEEE CAS
- IEEE CEDA
- IPSJ SIG-SLDM: Information Processing Society of Japan, SIG System LSI Design Methodology
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Association for Computing Machinery
New York, NY, United States
Publication History
Published: 21 January 2019
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ASPDAC '19
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ASPDAC '19: 24th Asia and South Pacific Design Automation Conference
January 21 - 24, 2019
Tokyo, Japan
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Overall Acceptance Rate 466 of 1,454 submissions, 32%
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ASPDAC '25
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Cited By
View all- Lyu LWang YChen CRichard Shi C(2020)A 0.6V 1.07 μW/Channel neural interface IC using level-shifted feedbackIntegration, the VLSI Journal10.1016/j.vlsi.2019.11.00170:C(51-59)Online publication date: 1-Jan-2020
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