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A wide conversion ratio, 92.8% efficiency, 3-level buck converter with adaptive on/off-time control and shared charge pump intermediate voltage regulator

Published: 21 January 2019 Publication History

Abstract

An efficient cascode 3-level buck converter with adaptive on/off-time (AOOT) control and shared charge pump (CP) intermediate voltage (Vmid) regulator is proposed and demonstrated. The conversion ratio (CR) Vout/Vin is enhanced by using the proposed AOOT control scheme, where the control switches between adaptive on-time (AOnT) and adaptive off-time (AOffT) mode according to the target CR. The proposed CP shares flying capacitor Cfly and power switches in the 3-level buck converter to generate Vmid=Vin/2 achieving both small size and low loss. The proposed 3-level buck converter is implemented in a standard 0.25μm CMOS process. 92.8% maximum efficiency and wide CR are obtained with the integrated Vmid regulator.

References

[1]
P. Kumar et al., IEEE CICC, 2015.
[2]
X. Liu et al., IEEE JSSC, vol. 53, pp. 582--595, 2018.
[3]
J. Xue et al., IEEE JSSC, vol. 51, pp. 2854--2866, 2016.
[4]
L. -C. Chu et al., IEEE ISSCC, pp. 186--187, 2017.
[5]
J. Xiao et al., IEEE JSSC, vol. 39, pp. 2342--2348, 2004.
[6]
P. Hazucha et al., IEEE JSSC, vol. 42, pp. 66--73, 2007.
[7]
Y. Karasawa et al., IEEE VLSI Circ., pp. 227--228, 2018.

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cover image ACM Conferences
ASPDAC '19: Proceedings of the 24th Asia and South Pacific Design Automation Conference
January 2019
794 pages
ISBN:9781450360074
DOI:10.1145/3287624
Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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  • IEICE ESS: Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
  • IEEE CAS
  • IEEE CEDA
  • IPSJ SIG-SLDM: Information Processing Society of Japan, SIG System LSI Design Methodology

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Association for Computing Machinery

New York, NY, United States

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Published: 21 January 2019

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