Article

Free access

The influences of fault type and topology on fault model performance and the implications to test and testable design

Authors:

Kenneth M. Butler,

M. Ray MercerAuthors Info & Claims

DAC '90: Proceedings of the 27th ACM/IEEE Design Automation Conference

Pages 673 - 678

https://doi.org/10.1145/123186.123436

Published: 03 January 1991 Publication History

Abstract

A new method, Difference Propagation, is proposed to analyze fault models in combinational circuits. It propagates Boolean functional information represented by ordered binary decision diagrams. Results are presented concerning exact detectabilities and syndromes for a set of benchmark circuits. The data suggest answers to open questions in CAD and represent the first data of this type for bridging faults. The information is shown to affect testable design as well as test generation.

References

[1]

J. P. Shen, W. Maly and F. J. Ferguson, "Inductive fault analysis of MOS integrated circuits," IEEE Design and Test of Comput., vo}. 2, no. 6, pp. 13-26, Dec. 1985.

Digital Library

[2]

J. L. A. Hughes and E. J. McCluskey, "Multiple stuck-at fault coverage of single stuck-at fault test sets," in Proc. 1986 IEEE Int. Test Conf., Sept. 1986, pp. 368-374.

[3]

S. D. Millman and E. J. McCluskey, "Detecting bridging faults with stuck-at test sets," in Proc. 1988 IEEE Int. Test Conf., Sept. 1988, pp. 773- 783.

Digital Library

[4]

F. Brglez and H. Fujiwara, "A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN," in Proc. IEEE int. Syrup. on Circ. Syst. (ISCAS), June 1985, pp. 695-698.

[5]

R. D. Eldred, "Test routines based on symbolic logical statements," J. Assoc. Comput. Mach., vol. 6, no. 1, pp. 33-36, 1959.

Digital Library

[6]

D. C. Bossen arid S. J. Hong, "Cause-effect analysis for multiple fault detection in combinational networks," tEEE Trans. Compu$., vol. C-20, no. 11, pp. 1252-1257, Nov. 1971.

[7]

E. J. McCluskey and F. W. Clegg, "Fault equivalence in combinational logic networks," IEEE Trans. Cornput., vol. C-20, no. 11, pp. 1286-1293, July 1971.

[8]

J. Galiay, Y. Crouzet and M. Vergniault, "Physical versus logical fault models MOS LSI circuits: impact on their testability," IEEE Trans. Cornput., vol. C-29, no. 6, pp. 527-531, June 1980.

[9]

K. C. Y. Mei, "Bridging and stuck-at faults," IEEE Trans. Comput., vol. C-23, no. 7, pp. 720- 727, July 1974.

[10]

M. Abramovici and P. R. Menon, "A practical approach to fault simulation and test generation for bridging faults," in Proc. 1983 IEEE In~. Test Conf., Oct. 1983, pp. 138-142.

[11]

J. Savir, "Syndrome-testable design of combinational circuits," IEEE Trans. Comput., vol. C-29, no. 6, pp. 442-451, June 1980.

[12]

J. A. Waicukauski, E. B. Eichelberger, D. Forlenza, E. Lindbloom and T. McCarthy, "Fault simulation for structured VLSI design," VLSI Systems Design, vol. 6, no. 12, pp. 20--32, Dec. 1985.

[13]

R. K. Gaede, D. E. Ross, M. R. Mercer and K. M. Butler, "CATAPULT: Concurrent automatic testing allowing parallelization and using limited topology," in Proc. ACM-IEEE 25th Design Automation Conf., June 1988, pp. 597-600.

Digital Library

[14]

D. Stannard and B. Kaminska, "Detection of hard faults in a combinational circuit using budget constraints," in Proc. 1988 IEEE Int. Test Conf., Sept. 1988, p. 999.

[15]

R. E. Bryant, "Graph-based algorithms for boolean function manipulation," IEEE Trans. Comput., vol. C-35, no. 8, pp. 677-692, Aug. 1986.

Digital Library

[16]

K. Cho and R. E. Bryant, "Test pattern generation for sequential MOS circuits by symbolic fault, simulation," in Proc. ACM-IEEE 26th Design Automation Conf., June 1989, pp. 418-423.

Digital Library

[17]

S. B. Akers, "On a theory of Boolean functions," J. Soc. Indust. Appl. Math., vol. 7, no. 4, pp. 487- 498, Dec. 1959.

[18]

P.R. Menon, "A simulation program for logic networks," Bell Telephone Labs. Internal Technical Memorandum, No. MM65-1271-3, Mar. 1965.

[19]

V. D. Agrawal, S. C. Seth and C. C. Chuang, "Probabilistically guided test generation," in Proc. IEEE Int. Syrup. on Circ. Syst. (ISCAS), June 1985, pp. 687-690.

[20]

D. E. Ross, personal communication, Aug. 1989.

[21]

C-T. Hung, K. M. Butler and M. R. Mercer, unpublished manuscript, Apr. 1989.

Cited By

Dworak JWicker JLee SGrimaila MMercer MButler KStewart BWang L(2001)Defect-Oriented Testing and Defective-Part-Level PredictionIEEE Design & Test10.1109/54.90282018:1(31-41)Online publication date: 1-Jan-2001
https://dl.acm.org/doi/10.1109/54.902820
Grimaila MLee SDworak JButler KStewart BBalachandran HHouchins BMathur VPark JWang LMercer M(1999)REDO - Probabilistic Excitation and Deterministic Observation - First Commercial ExperimentProceedings of the 1999 17TH IEEE VLSI Test Symposium10.5555/832299.836541Online publication date: 26-Apr-1999
https://dl.acm.org/doi/10.5555/832299.836541
Zhang ZMcLeod RBridges G(1996)Statistical estimation of delay fault detectabilities and fault gradingJournal of Electronic Testing: Theory and Applications10.1007/BF001360758:1(47-60)Online publication date: 1-Feb-1996
https://dl.acm.org/doi/10.1007/BF00136075
Show More Cited By

Index Terms

The influences of fault type and topology on fault model performance and the implications to test and testable design
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design
2. Hardware

Recommendations

Design of Testable Adder in Quantumdot Cellular Automata with Fault Secure Logic

The rapid advancement of Quantum-dot cellular automata (QCA) technology has moved on to the effective methods for testing these circuits due to its insufficient reliability. The growing demand for fault tolerance and testability attracts more research ...
Design of Testable Reversible Sequential Circuits

In this paper, we propose the design of two vectors testable sequential circuits based on conservative logic gates. The proposed sequential circuits based on conservative logic gates outperform the sequential circuits implemented in classical gates in ...
Test patterns for fault-tolerant logic circuits using block design concepts
ACMSE '92: Proceedings of the 30th annual ACM Southeast Regional Conference

Fault-tolerant logic circuits have been considered untestable due to the redundancy introduced into the logic circuits to mask faults. Recently, the block design concepts have been used to construct system and gate level fault-tolerant logic circuits and ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

DAC '90: Proceedings of the 27th ACM/IEEE Design Automation Conference

January 1991

742 pages

ISBN:0897913639

DOI:10.1145/123186

Chairman:
Richard C. Smith

Copyright © 1991 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS: Computer Society

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 03 January 1991

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

DAC90

Sponsor:

SIGDA
IEEE-CS

DAC90: The 27th ACM/IEEE-CS Design Automation Conference

June 24 - 27, 1990

Florida, Orlando, USA

Acceptance Rates

DAC '90 Paper Acceptance Rate 125 of 427 submissions, 29%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

6
Total Citations
View Citations
270
Total Downloads

Downloads (Last 12 months)22
Downloads (Last 6 weeks)3

Reflects downloads up to 03 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

Dworak JWicker JLee SGrimaila MMercer MButler KStewart BWang L(2001)Defect-Oriented Testing and Defective-Part-Level PredictionIEEE Design & Test10.1109/54.90282018:1(31-41)Online publication date: 1-Jan-2001
https://dl.acm.org/doi/10.1109/54.902820
Grimaila MLee SDworak JButler KStewart BBalachandran HHouchins BMathur VPark JWang LMercer M(1999)REDO - Probabilistic Excitation and Deterministic Observation - First Commercial ExperimentProceedings of the 1999 17TH IEEE VLSI Test Symposium10.5555/832299.836541Online publication date: 26-Apr-1999
https://dl.acm.org/doi/10.5555/832299.836541
Zhang ZMcLeod RBridges G(1996)Statistical estimation of delay fault detectabilities and fault gradingJournal of Electronic Testing: Theory and Applications10.1007/BF001360758:1(47-60)Online publication date: 1-Feb-1996
https://dl.acm.org/doi/10.1007/BF00136075
Wang LMercer MWilliams T(1995)Enhanced testing performance via unbiased test setsProceedings of the 1995 European conference on Design and Test10.5555/787258.787518Online publication date: 6-Mar-1995
https://dl.acm.org/doi/10.5555/787258.787518
Sastry SMajumdar ANewton A(1991)A branching process model for observability analysis of combinational circuitsProceedings of the 28th ACM/IEEE Design Automation Conference10.1145/127601.127711(452-457)Online publication date: 1-Jun-1991
https://dl.acm.org/doi/10.1145/127601.127711
Ross DBulter KMercer M(1991)Exact ordered binary decision diagram size when representing classes of symmetric functionsJournal of Electronic Testing: Theory and Applications10.1007/BF001354412:3(243-259)Online publication date: 1-Sep-1991
https://dl.acm.org/doi/10.1007/BF00135441

View Options

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

Media

Figures

Other

Tables

View Table of Contents