We're #hiring a new Embedded Technology Coordinator in Austin, Texas. Apply today or share this post with your network.
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We're looking for a Senior Embedded Software Engineer to join our team at Vicarious Surgical. This is a fantastic opportunity to contribute to groundbreaking healthcare advancements through state-of-the-art medical devices. If you're driven by a passion for improving patient care and pushing the boundaries of medical technology, we want to hear from you! Apply now: https://ow.ly/CBAv50ShX0e #NowHiring #MedicalRobotics #HealthcareInnovation
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TL; DR - apple is hiring chip design engineers for SOC group. PM me if relevant. I have started working in apple ~7 months ago. I have not updated my profile right from the start , and since the war broke out with Hamas's barbaric attack, I found it difficult to discuss work matters while our soldiers are still fighting to protect us. I have decided to post now that our team is hiring, as I feel this is the little help I can offer in these challenging times. Please see the position below and PM if you find it relevant and want to apply. P.S. a few words about working at apple: A motto that I heard here is that you come to apple to do "your best work". I found it true for me, as the environment here fosters efficiency and productivity while also being considerate of these hard times and allowing work-life balance (I am currently on special apple paternity leave).
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New role! Field Application Engineer, Up to $300k OTE! (depending on experience) - #SanFrancisco. Interested? Click the link to apply #ProductManager #sales #SaaS #marketing #presales #TechnologyCareers #TechnologyJobs #software #VRWearables #ProductMarketing #XR #simulationsoftware #IP #VirtualReality #AugmentedReality #EDA #semiconductors #businessdeveloper #AI #Metaverse #salesrecruitment #ICResources #TechnologyRecruitment #electronics #Web3
Field Application Engineer
ic-resources.com
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Share Google hiring info and feel free to ping me if you have any question.
Expand Your Career with Google Silicon and CPU Teams. We’re growing in #Taiwan and #hiring for key roles in #performance and power #architecture, #RTL design, Design Verification (#DV), #physical design, #CAD, #compiler, #ATE, #CPU, #SOC and #software areas. Apply Now: https://lnkd.in/gwhq9R38 Let's build the future of computing together.
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Opportunity
Hiring Sales Manger,Design Engineers and Embedded System Engineers Apply today : [email protected]
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Good opportunity
I am looking for an experienced(~8 to 10 years) DV engineer with prior experience of working on compute subsystems like CPU, GPU, DSP etc. People who fit the requirement please message me your resume. #hiring #verification #machinelearning
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#hiring Senior Principal Engineer - Signoff, San Jose, United States, fulltime #jobs #jobseekers #careers #SanJosejobs #Californiajobs Apply: https://lnkd.in/d3JpHyAn Job Overview: Arm has formed a new group to develop outstanding silicon demonstrators based on Arm's IP compute sub-system solutions and addressing markets such as premium mobile, infrastructure and automotive. Using the latest nodes, e.g. 3nm today, and applying the latest SoC 2.5D and 3D technology, Arm's ambition is to demonstrate industry outstanding performance by architecting, designing, implementing, and fabricating innovative silicon chips. Responsibilities: Your responsibilities will involve developing challenging electrical signoff methodologies. These methodologies will balance accuracy and yield on silicon. The following are the immediate challenges we will be working on as a team: We will develop a Static Timing Analysis flow that is standardized and is usable by all silicon groups within Arm We will work on strengthening our methodologies to analyze static and dynamic IR drop on the SoC. We will release a qualified flow that enable STA with back annotated voltage Electromigration analysis at the SoC level is another key responsibility of this role. Including Local thermal effects as part of electromigration analysis is a key criteria! Soft Error rate is a key concern for Infrastructure and Automotive SoC's. We will develop methodologies to analyze and alleviate the impact of Soft Error rate on SoC's Required Skills and Experience : Experience in developing Signoff methodologies such as Aging, STA, EM IR in advanced process nodes. Experience in collaborating across silicon engineering groups in your organization as well as with EDA vendors Work experience in Physical Implementation and Signoff methodologies Must have worked on methodology development on 5nm or 3nm technologies Strong data analysis skills to fetch data, analyze and provide practical insights "Nice To Have" Skills and Experience : Masters in Electrical Engineering Strong coding skills in Python or R or an equivalent language Strong presentation skills Salary Range From $2 46,925.00 To $ 319,550.00 We value people as individuals and our commitment is to reward people competitively and equitably for the work they do and the skills and experience they bring to Arm. Salary is only one component of Arm's offering. The total reward package will be shared with candidates during the recruitment and selection process. In Return: We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.
https://www.jobsrmine.com/us/california/san-jose/senior-principal-engineer-signoff/464053363
jobsrmine.com
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#hiring Senior Principal Engineer - Signoff, San Jose, United States, fulltime #jobs #jobseekers #careers #SanJosejobs #Californiajobs #Engineering Apply: https://lnkd.in/g_AhNagM Job Overview: Arm has formed a new group to develop outstanding silicon demonstrators based on Arm's IP compute sub-system solutions and addressing markets such as premium mobile, infrastructure and automotive. Using the latest nodes, e.g. 3nm today, and applying the latest SoC 2.5D and 3D technology, Arm's ambition is to demonstrate industry outstanding performance by architecting, designing, implementing, and fabricating innovative silicon chips. Responsibilities: Your responsibilities will involve developing challenging electrical signoff methodologies. These methodologies will balance accuracy and yield on silicon. The following are the immediate challenges we will be working on as a team: We will develop a Static Timing Analysis flow that is standardized and is usable by all silicon groups within Arm We will work on strengthening our methodologies to analyze static and dynamic IR drop on the SoC. We will release a qualified flow that enable STA with back annotated voltage Electromigration analysis at the SoC level is another key responsibility of this role. Including Local thermal effects as part of electromigration analysis is a key criteria! Soft Error rate is a key concern for Infrastructure and Automotive SoC's. We will develop methodologies to analyze and alleviate the impact of Soft Error rate on SoC's Required Skills and Experience : Experience in developing Signoff methodologies such as Aging, STA, EM IR in advanced process nodes. Experience in collaborating across silicon engineering groups in your organization as well as with EDA vendors Work experience in Physical Implementation and Signoff methodologies Must have worked on methodology development on 5nm or 3nm technologies Strong data analysis skills to fetch data, analyze and provide practical insights "Nice To Have" Skills and Experience : Masters in Electrical Engineering Strong coding skills in Python or R or an equivalent language Strong presentation skills Salary Range From $2 46,925.00 To $ 319,550.00 We value people as individuals and our commitment is to reward people competitively and equitably for the work they do and the skills and experience they bring to Arm. Salary is only one component of Arm's offering. The total reward package will be shared with candidates during the recruitment and selection process. In Return: We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.
https://www.jobsrmine.com/us/california/san-jose/senior-principal-engineer-signoff/465465661
jobsrmine.com
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#hiring Senior Principal Engineer - Signoff, San Jose, United States, fulltime #jobs #jobseekers #careers #SanJosejobs #Californiajobs #Engineering Apply: https://lnkd.in/gXvKX_8c Job Overview: Arm has formed a new group to develop outstanding silicon demonstrators based on Arm's IP compute sub-system solutions and addressing markets such as premium mobile, infrastructure and automotive. Using the latest nodes, e.g. 3nm today, and applying the latest SoC 2.5D and 3D technology, Arm's ambition is to demonstrate industry outstanding performance by architecting, designing, implementing, and fabricating innovative silicon chips. Responsibilities: Your responsibilities will involve developing challenging electrical signoff methodologies. These methodologies will balance accuracy and yield on silicon. The following are the immediate challenges we will be working on as a team: We will develop a Static Timing Analysis flow that is standardized and is usable by all silicon groups within Arm We will work on strengthening our methodologies to analyze static and dynamic IR drop on the SoC. We will release a qualified flow that enable STA with back annotated voltage Electromigration analysis at the SoC level is another key responsibility of this role. Including Local thermal effects as part of electromigration analysis is a key criteria! Soft Error rate is a key concern for Infrastructure and Automotive SoC's. We will develop methodologies to analyze and alleviate the impact of Soft Error rate on SoC's Required Skills and Experience : Experience in developing Signoff methodologies such as Aging, STA, EM IR in advanced process nodes. Experience in collaborating across silicon engineering groups in your organization as well as with EDA vendors Work experience in Physical Implementation and Signoff methodologies Must have worked on methodology development on 5nm or 3nm technologies Strong data analysis skills to fetch data, analyze and provide practical insights "Nice To Have" Skills and Experience : Masters in Electrical Engineering Strong coding skills in Python or R or an equivalent language Strong presentation skills Salary Range From $2 46,925.00 To $ 319,550.00 We value people as individuals and our commitment is to reward people competitively and equitably for the work they do and the skills and experience they bring to Arm. Salary is only one component of Arm's offering. The total reward package will be shared with candidates during the recruitment and selection process. In Return: We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.
https://www.jobsrmine.com/us/california/san-jose/senior-principal-engineer-signoff/466309059
jobsrmine.com
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Apply now! Field Application Engineer, Up to $300k OTE! (depending on experience) - #SanFrancisco. Interested? Click the link to apply #TechnologyJobs #marketing #SaaS #Metaverse #businessdeveloper #VRWearables #semiconductors #XR #TechnologyCareers #electronics #ICResources #ProductManager #presales #EDA #ProductMarketing #TechnologyRecruitment #sales #AI #AugmentedReality #Web3 #VirtualReality #salesrecruitment #software #IP #simulationsoftware
Field Application Engineer
ic-resources.com
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