Milos Mirosavljevic’s Post

𝙑𝙀𝙍𝙄𝙁𝙄𝘾𝘼𝙏𝙄𝙊𝙉 𝘿𝙄𝘼𝙍𝙄𝙀𝙎 #1 📖 📒 📓 I asked Anja Planić, one of our verification team leaders here at Vtool - Smart Verification, what part of IP verification she loves the most. "𝑻𝒉𝒆 𝒎𝒐𝒔𝒕 𝒊𝒏𝒕𝒆𝒓𝒆𝒔𝒕𝒊𝒏𝒈 𝒑𝒂𝒓𝒕 𝒇𝒐𝒓 𝒎𝒆 𝒊𝒔 𝒕𝒉𝒆 𝒄𝒓𝒆𝒂𝒕𝒊𝒗𝒊𝒕𝒚 𝒊𝒏 𝒊𝒎𝒑𝒍𝒆𝒎𝒆𝒏𝒕𝒊𝒏𝒈 𝒒𝒖𝒂𝒍𝒊𝒕𝒚 𝒄𝒐𝒅𝒆 𝒂𝒏𝒅 𝒕𝒉𝒆 𝒑𝒐𝒘𝒆𝒓 𝒐𝒇 𝒊𝒕𝒔 𝒓𝒆𝒖𝒔𝒂𝒃𝒊𝒍𝒊𝒕𝒚 𝒇𝒐𝒓 𝒕𝒉𝒆 𝒑𝒂𝒓𝒕𝒊𝒄𝒖𝒍𝒂𝒓 𝑰𝑷 𝒊𝒏 𝒕𝒉𝒆 𝒔𝒚𝒔𝒕𝒆𝒎𝒔. 𝑽𝒆𝒓𝒊𝒇𝒚𝒊𝒏𝒈 𝒂𝒏 𝑰𝑷 𝒈𝒊𝒗𝒆𝒔 𝒂𝒏 𝒆𝒏𝒈𝒊𝒏𝒆𝒆𝒓 𝒂 𝒎𝒐𝒓𝒆 𝒅𝒆𝒕𝒂𝒊𝒍𝒆𝒅 𝒆𝒙𝒑𝒍𝒐𝒓𝒂𝒕𝒊𝒐𝒏 𝒂𝒏𝒅 𝒂 𝒇𝒐𝒄𝒖𝒔 𝒐𝒏 𝒆𝒗𝒆𝒓𝒚 𝒅𝒆𝒕𝒂𝒊𝒍, 𝒘𝒉𝒊𝒄𝒉 𝒄𝒂𝒏 𝒈𝒓𝒆𝒂𝒕𝒍𝒚 𝒔𝒊𝒎𝒑𝒍𝒊𝒇𝒚 𝒕𝒉𝒆 𝒑𝒓𝒐𝒄𝒆𝒔𝒔 𝒐𝒇 𝒗𝒆𝒓𝒊𝒇𝒚𝒊𝒏𝒈 𝒄𝒐𝒎𝒑𝒍𝒆𝒙 𝒅𝒆𝒔𝒊𝒈𝒏𝒔 𝒖𝒏𝒅𝒆𝒓 𝒕𝒆𝒔𝒕." Stay tuned for more stories to come. #verificationengineer #diaries #verification #bestjobever #stories ---------------------------------------- In this series, I am asking verification engineers about various aspects of their jobs. My hope is that their stories will inspire more people to truly appreciate how the job of verification engineer is interesting, challenging, and at the end of the day, very fulfilling.

Want to work as a Design & Verification Engineer ? In this video we have discussed ->The skills required to become a professional design & verification engineer. ->Vast opportunities in Design & Verification ->Who should opt for Design & Verification domain? **REGISTRATION OPEN for upcoming Design & Verification Course. (Link in comments) If you have any questions, feel free to ask them in comments.

5 Mistakes I made as a Verification Engineer Someone recently asked me about my experience working as a Verification engineer and if I have any advice to share to engineers starting now. I thought it would be better if I shared some of the silly mistakes I made back then. These are things I’ve learned to improve over time especially points 2 and 5 - which weren’t very clear to me at first. I still remember filing bugs without going too deep in the RTL and sometimes getting my analysis completely wrong. I also used to delete passing logs and coverage files too soon - struggling to provide results later when asked. Does this sound relatable? I’m sure you’ve made your own mistakes—comment below! 😄 #servingTheNextBug #lowpowerdesign #verification #semiconductors #verificationengineer

VErification

Verification

𝑭𝒓𝒆𝒒𝒖𝒆𝒏𝒕 𝒎𝒊𝒔𝒕𝒂𝒌𝒆 𝒗𝒆𝒓𝒊𝒇𝒊𝒄𝒂𝒕𝒊𝒐𝒏 𝒆𝒏𝒈𝒊𝒏𝒆𝒆𝒓𝒔 𝒎𝒂𝒌𝒆 is not 𝐢𝐧𝐬𝐢𝐬𝐭𝐢𝐧𝐠 on having their test plan reviewed. In theory, the architect should approve every verification plan. However, this often doesn't happen for many reasons. The most common one is an architect's lack of time. Another reason is that the verification engineer is "trusted" to have covered everything relevant. This approach can lead to severe problems down the road, such as realizing you didn't verify that one clear-on-read register that buried somewhere deep in the RTL. I strongly advise all verification engineers I work with to insist on having their test plan reviewed and approved. If this is not possible, raise a flag and say that it may lead to problems later on. #verification #verificationengineer #testplan #verificationplan #success #persistence

Verification

As a verification engineer, I believe that debugging issues in a code that uses bad or confusing naming convention this may rank first in the most intense pain, surpassing toothache and the pain of stubbing your little toe on a furniture! #functionalVerification

Looking to apply formal verification on your design? Here are some tips that can help 1. Understand Formal Verification: Recognize it as a mathematical analysis of a design's possible behaviors. Different from simulation which tests specific values, formal verification ensures comprehensive coverage. 2. Use Appropriate Tools: Tools like Jasper can visualize reaching specific states without predefined inputs. These tools compute necessary inputs, simplifying error checking and validation. 3. Leverage Advantages: Formal verification covers the entire behavior space, finding corner cases. Dynamic debugging allows live adjustments and scenario modifications. 4. Integrate into Workflow: Apply formal verification from early RTL modeling to post-silicon debugging. Utilize applications like property verification, equivalence checking, and connectivity verification. 5. Adopt a New Mindset: Shift from simulation-driven testing to formal methods. Address concerns about complexity, coverage, and training through targeted use and training. 6. Maximize Benefits: Achieve systematic, thorough validation with less effort. Increase productivity and detect bugs earlier. Use formal verification where possible, and simulate only when necessary. #FormalVerification #DesignProductivity #Validation #Simulation #RTLModeling #Debugging #Engineering #TechTips #VerificationTools #JasperTool #CircuitDesign https://lnkd.in/gVpAj8b2