Ani Marellapudi

  I am sharing thoughts on Greg Edlund’s book “Timing Analysis and Simulation for Signal Integrity Engineers”. Like Greg’s work, his book is very detailed. Starting simply with Flip Flops then moving onto common clock and source synchronous timing. Giving some excellent SI background and examples he explores T-lines, crosstalk, channel step response, Jitter, Eye diagrams DDR and PCIE case studies, and even a CMOS and SPICE primer. His book is very practical for any SI engineer who wants to brush up on timing analysis and SI. Greg and I worked closely together at DEC, and I appreciate his acknowledgement in his book. We were working on a next generation Alpha-Server when he joined the SI group with a background of BS in Physics, versus most SI Engineers were EE’s or ECE (Electrical and Computer Engineering). Greg had a great work ethic and was in early and worked a full day. I credit him with giving me the technical writing bug and introducing me to DesignCon (originally SuperCon). We worked long and hard on our “Constructing Accurate Behavioral Buffers” Paper for DesignCon 98, which won best paper tied to a Demo. I wrote the first half, while Greg wrote the second half. His wife was an English major and our editor. Together we also designed a SI test chip and PCB to examine Simultaneous Switching noise and ground bounce on the Motorola's MCA (Macro Cell Array) package and IC, that we would be utilizing in our next server. We lab validated all our behavioral (SEIN/IBIS) models and brought the 8400 AlphaServer from power-on to full-speed operation in less than one week. After Greg left DEC, I had to clean out his desk, it was the most organized file cabinet I had ever seen in my life. The first static timing tool I ever used Topaz (DEC internal). Eventually I phased over to Blast (Vendor tool). After discussing issues with the SW Vendors lead Timing Engineer, she said she made my EDN Feature Article “The Nuts and Bolts of Signal Integrity Analysis” required reading for her entire group. https://lnkd.in/ec7P9yrH Working as a SI Consultant/Super AE for SISOFT I taught customer classes on static timing analysis (source synchronous and common clock) including deriving all the timing equations from scratch on the white board.

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Check out the latest episode of the #PrintedCircuitPodcast where Daniel Beeker shares with me his awesome insights on his favorite subjects: PDNs and space. Great words of wisdom from Dan, who is an industry leader and subject matter expert! Come meet up with us in person at PCB East in June! 😉 #PrinetdCircuitPodcast #PCBDeisgn #PDN #Space

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The Beta-Multiplier is the core of many CMOS voltage and current references. - However, designing for nA-range currents requires a gigantic resistor. - One possible solution is to replace the resistor by a transistor operating in the linear region [1]. - By intelligently biasing the transistor, one can obtain a fairly stable current reference, for a much lower area than that of a polysilicon resistor. What do you think are the pros/cons of implementing a resistor-less beta-multiplier? By the way, it is also interesting to think about the difference in the conventional beta-multiplier, if we short the drain-gate of M2 & M4 instead of M1 & M3. I covered it in one of my earlier videos: Loop Gain of Bandgap Core https://lnkd.in/gpKVdTPk Reference [1]: https://lnkd.in/gC-6CjDn #analog #circuits #vlsi #bandgap #cmos #semiconductor

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6 Steps of Semiconductor Testing (for non-engineers): 🔍 Wafer Probing: Imagine a large circular slice of semiconductor material loaded with countless tiny electronic chips. Wafer probing is like giving each chip a quick check-up before they're separated and packaged. It ensures they're working correctly right from the start, like a preliminary health screening for electronics! 💡 Fine Pitch & Micro Bumped Wafers: To pack more circuits into smaller spaces, engineers use innovative techniques like fine pitch and micro bumped wafers. Think of it as fitting more passengers onto a bus without overcrowding – it's about maximizing efficiency and space utilization on the semiconductor wafer. 🔌 DC to Full RF Probing: Now, let's talk about the tools used in wafer probing – probe cards. These nifty gadgets are designed to handle various electrical signals, from the steady flow of Direct Current (DC) to the speedy transmissions of Radio Frequency (RF). It's like having a versatile tool belt for testing electronic circuits of all kinds! 🚀 High Multisites Testing: Testing one chip at a time is efficient, but testing multiple chips simultaneously is even better! High multisites testing allows engineers to check several chips on the same wafer at once, speeding up the process like scanning multiple items at a grocery store checkout. Efficiency at its finest! 📊 Wafer Sorting Interface: Once the chips are probed and tested, it's time to sort them based on their performance and quality. This process is akin to grading exam papers – chips that meet the standards get a pass, while those that fall short are flagged for further inspection or adjustments. It's all about ensuring only the best chips make it to the final product! 🔬 Final Testing: Before the chips are packaged and shipped off to power our devices, they undergo one last round of rigorous testing. This final check ensures that each chip meets the highest standards of quality and reliability. It's like the grand finale of a fireworks show – a dazzling display of precision and perfection! For opportunities to work on semiconductor test processes, contact us at DELVE Search! #semiconductor #semiconductorjobs #semiconductortest #osat #advancedpackaging

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Decoding Lithium-Ion Battery Behavior through Equivalent Circuit Models When it comes to optimizing lithium-ion battery performance, understanding their internal dynamics is key. Equivalent circuit models are powerful tools that help us simulate and predict how a battery responds under different conditions, guiding the design of more efficient and reliable battery systems. Several models are commonly used: 1. Open Circuit Voltage (OCV) Model: This simplest model assumes the battery voltage remains constant, providing a basic starting point for understanding battery behavior. It’s a great way to grasp the fundamentals, though it doesn't capture dynamic responses. 2. State of Charge (SOC) Model: SOC models track the battery’s charge level, showing how voltage changes with charging and discharging. This is crucial for applications where knowing the exact charge level is essential, such as in electric vehicles. 3. Internal Resistance (Rint) Model: Here, we account for the battery’s internal resistance, which affects voltage drop and power loss. This model is particularly useful for low-power applications, though more advanced scenarios require additional detail. 4. Thevenin Model: By incorporating parallel resistor-capacitor circuits, the Thevenin model offers a more sophisticated approximation of real-world battery behavior, including how the battery voltage changes dynamically with current flow. 5. Randles Model: This model dives into the electrochemical processes inside the battery, using elements like charge-transfer resistance and double-layer capacitance to simulate more complex interactions. It’s a preferred choice for understanding how batteries perform under varying load conditions. Equivalent circuit models are more than just theoretical constructs—they are practical tools that engineers use to enhance battery performance, predict lifespan, and improve safety. By leveraging these models, we can push the boundaries of what's possible with lithium-ion batteries, from consumer electronics to electric vehicles. #BatteryTechnology #LithiumIon #ElectricVehicles #EnergyStorage #Engineering #Innovation #ev #lithium

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