Abstract
A new window-opening low-power area-efficient switching logic for high speed successive approximation register (SAR) analog-to-digital converter (ADC) is proposed in this paper. Unlike conventional SAR logic based on the shift register, the window-opening scheme minimizes the delay by putting the comparator results almost directly to DAC, and utilizes domino-based structure to reduce the capacitive load for comparator. According to pre-layout simulation in 65 nm CMOS technology, a 10 bit 100 MS/s SAR ADC with the new logic achieves a logic delay of 73 ps including DAC buffer delay, which is much lower than most SAR ADC.
