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VISA: A variable instruction set architecture

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Alessandro De GloriaAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 18, Issue 2

Pages 76 - 84

https://doi.org/10.1145/88237.88245

Published: 01 May 1990 Publication History

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Abstract

This paper presents an instruction coding technique that allows to reduce the instruction width without limiting the exploitation of the machine resources. This result can be obtained by a dynamic instruction coding managed by the compiler.The technique has been applied to a VLIW-structured machine. The machine has an instruction width of 32 bits, while the number of bits needed to code all the functions the machine can perform in a cycle is 98.

References

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2 D. Patterson and C. Sequin, "A VLSI RISC", Computer, September, 1982, pp. 8-21.

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[3]

3 J.L. Hennessy, "VLSI Processor Architecture", IEEE Trans. on Computer, C-33, pp. 1221-1246, Dec. 1984.

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4 J. Fisher, "Trace Scheduling: A technique for global microcode compaction", IEEE Trans. on Computer, C-30, pp. 478-490, July 1981.

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5 J.R. Ellis, "Bulldog: A compiler for VLIW Architecture", MIT Press, Cambridge, Massachussets, 1986.

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6 R. Colwell, R. Nix, J. O'Donnel, D. Papworth, R. Rodman, "A VLIW Architecture for Trace Scheduling Compiler", Proc. of ASPLOS, Palo Alto, Oct. 1987.

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7 F. Chow, S. Correll, M. Himelstein, E. Killian, L. Weber, "How many addressing modes are enough?" Proc. of AS PLOS, Palo Alto, Oct. 1987.

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Cited By

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Fournaris AKeramidas GIspoglou KVoros N(2016)VirISA: Recruiting Virtualization and Reconfigurable Processor ISA for Malicious Code Injection ProtectionComponents and Services for IoT Platforms10.1007/978-3-319-42304-3_7(117-130)Online publication date: 24-Sep-2016
https://doi.org/10.1007/978-3-319-42304-3_7
Patil SMuthukumar V(2008)Maximizing Resource Utilization by Slicing of Superscalar ArchitectureProceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools10.1109/DSD.2008.125(923-930)Online publication date: 3-Sep-2008
https://dl.acm.org/doi/10.1109/DSD.2008.125

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VISA: A variable instruction set architecture

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Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 18, Issue 2

Jun. 1990

83 pages

ISSN:0163-5964

DOI:10.1145/88237

Editor:
Doug DeGroot
Texas Instruments, Inc., Dallas, TX

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Association for Computing Machinery

New York, NY, United States

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Published: 01 May 1990

Published in SIGARCH Volume 18, Issue 2

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Fournaris AKeramidas GIspoglou KVoros N(2016)VirISA: Recruiting Virtualization and Reconfigurable Processor ISA for Malicious Code Injection ProtectionComponents and Services for IoT Platforms10.1007/978-3-319-42304-3_7(117-130)Online publication date: 24-Sep-2016
https://doi.org/10.1007/978-3-319-42304-3_7
Patil SMuthukumar V(2008)Maximizing Resource Utilization by Slicing of Superscalar ArchitectureProceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools10.1109/DSD.2008.125(923-930)Online publication date: 3-Sep-2008
https://dl.acm.org/doi/10.1109/DSD.2008.125

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Abstract

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Recommendations

Automatic custom instruction identification for application-specific instruction set processors

Increasing the instruction fetch rate via block-structured instruction set architectures

Block-aware instruction set architecture

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