Article

Reconfigurable SoC design with hierarchical FSM and synchronous dataflow model

Authors:

Kiyoung ChoiAuthors Info & Claims

CODES '02: Proceedings of the tenth international symposium on Hardware/software codesign

Pages 199 - 204

https://doi.org/10.1145/774789.774830

Published: 06 May 2002 Publication History

Abstract

We present a method of runtime configuration scheduling in reconfigurable SoC design. As a model of computation in system representation, we use a popular formal model of computation, hierarchical FSM (HFSM) with synchronous dataflow (SDF) model, in short HFSM-SDF model. In reconfigurable SoC design with the HFSM-SDF model, the problem of configuration scheduling is challenging due to the dynamic behavior of the system such as concurrent execution of state transitions (by AND relation), complex flow (in the HFSM), and complex schedules of SDF actor firing. Thus, compile-time static configuration scheduling may not efficiently hide configuration latency.To resolve the problem, it is necessary to know the exact order of required configurations during runtime and to perform runtime configuration scheduling. To obtain the exact order of configuration, we exploit the inherent property of HFSM-SDF that the execution order of SDF actors can be determined before the execution of state transition of top FSM. After obtaining the order information in a queue called ready configuration queue, we execute the state transition. During the execution, whenever there is new available FPGA resource, a new configuration is selected from the queue and fetched by the runtime configuration scheduler. We applied the method to an MPEG4 decoder design and obtained up to 21.8% improvement in system runtime with a negligible overhead of runtime (1.4%) and memory usage (0.94%).

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Cited By

Sklyarov VSkliarova I(2013)High-Performance Data Processing Over N-ary TreesHigh-Performance Computing Using FPGAs10.1007/978-1-4614-1791-0_8(245-277)Online publication date: 28-Feb-2013
https://doi.org/10.1007/978-1-4614-1791-0_8
Sklyarov VSkliarova IMihhailov DSudnitson A(2010)Synthesis and Implementation of Hierarchical Finite State Machines with Implicit ModulesProceedings of the 2010 International Conference on Reconfigurable Computing and FPGAs10.1109/ReConFig.2010.29(436-441)Online publication date: 13-Dec-2010
https://dl.acm.org/doi/10.1109/ReConFig.2010.29
Ou JMuhammad FHaase JGrimm C(2010)A formal model for specification and optimization of flexible communication systems2010 NASA/ESA Conference on Adaptive Hardware and Systems10.1109/AHS.2010.5546253(241-249)Online publication date: Jun-2010
https://doi.org/10.1109/AHS.2010.5546253
Show More Cited By

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Reconfigurable SoC design with hierarchical FSM and synchronous dataflow model

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Published In

cover image ACM Conferences

CODES '02: Proceedings of the tenth international symposium on Hardware/software codesign

May 2002

232 pages

ISBN:1581135424

DOI:10.1145/774789

General Chairs:
Joerg Henkel
C & C Research Labs, NEC
,
Xiaobo Sharon Hu
University of Notre Dame
,
Program Chairs:
Rajesh Gupta
University of California, Irvine
,
Sri Parameswaran
University of New South Wales, Australia

Copyright © 2002 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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IFIP WG 10.5: IFIP WG 10.5
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SIGDA: ACM Special Interest Group on Design Automation
SIGSOFT: ACM Special Interest Group on Software Engineering
IEEE-CS\DATC: IEEE Computer Society

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 06 May 2002

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CODES02: 10th International Symposium on Hardware/Software Codesign

May 6 - 8, 2002

Colorado, Estes Park

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Cited By

Sklyarov VSkliarova I(2013)High-Performance Data Processing Over N-ary TreesHigh-Performance Computing Using FPGAs10.1007/978-1-4614-1791-0_8(245-277)Online publication date: 28-Feb-2013
https://doi.org/10.1007/978-1-4614-1791-0_8
Sklyarov VSkliarova IMihhailov DSudnitson A(2010)Synthesis and Implementation of Hierarchical Finite State Machines with Implicit ModulesProceedings of the 2010 International Conference on Reconfigurable Computing and FPGAs10.1109/ReConFig.2010.29(436-441)Online publication date: 13-Dec-2010
https://dl.acm.org/doi/10.1109/ReConFig.2010.29
Ou JMuhammad FHaase JGrimm C(2010)A formal model for specification and optimization of flexible communication systems2010 NASA/ESA Conference on Adaptive Hardware and Systems10.1109/AHS.2010.5546253(241-249)Online publication date: Jun-2010
https://doi.org/10.1109/AHS.2010.5546253
Czarnecki RDeniziak S(2007)Resource Constrained Co-synthesis of Self-reconfigurable SOPCs2007 IEEE Design and Diagnostics of Electronic Circuits and Systems10.1109/DDECS.2007.4295253(1-6)Online publication date: Apr-2007
https://doi.org/10.1109/DDECS.2007.4295253
Liu ZArslan TKhawam SLindsay ITang T(2005)A high performance synthesisable unsymmetrical reconfigurable fabric for heterogeneous finite state machinesProceedings of the 2005 Asia and South Pacific Design Automation Conference10.1145/1120725.1120983(639-644)Online publication date: 18-Jan-2005
https://dl.acm.org/doi/10.1145/1120725.1120983
Zhenyu Liu Arslan TKhawam SLindsay I(2005)A high performance synthesisable unsymmetrical reconfigurable fabric for heterogeneous finite state machinesProceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.10.1109/ASPDAC.2005.1466242(639-644)Online publication date: 2005
https://doi.org/10.1109/ASPDAC.2005.1466242
Choi MPark NPiuri VLombardi F(2004)Evaluating the Repair of System-on-Chip (SoC) Using ConnectivityIEEE Transactions on Instrumentation and Measurement10.1109/TIM.2004.83460353:6(1464-1472)Online publication date: Dec-2004
https://doi.org/10.1109/TIM.2004.834603
Silva JCosta RJorge G(2003)RtrASSoc: an adaptable superscalar reconfigurable system-on-chip. The simulatorThe 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.10.1109/IWSOC.2003.1213034(196-200)Online publication date: 2003
https://doi.org/10.1109/IWSOC.2003.1213034
Choi MPark NPiuri VKim YLombardi F(2003)Evaluating the repair of system-on-chip (soc) using connectivityProceedings of the 20th IEEE Instrumentation Technology Conference (Cat. No.03CH37412)10.1109/IMTC.2003.1208172(309-314)Online publication date: 2003
https://doi.org/10.1109/IMTC.2003.1208172

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