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An integrated floorplanning with an efficient buffer planning algorithm

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Jun GuAuthors Info & Claims

ISPD '03: Proceedings of the 2003 international symposium on Physical design

Pages 136 - 142

https://doi.org/10.1145/640000.640031

Published: 06 April 2003 Publication History

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Abstract

Previous works on buffer planning are mainly based on fixed die placement. It is necessary to reduce the complexity of computing the feasible buffer insertion sites to integrate the buffer planning with the floorplanning process. In this paper, we give an efficient buffer planning algorithm with linear complexity by computing all the feasible buffer insertion sites in a 2-step method. By partitioning all the dead spaces into blocks while doing the packing, the buffer allocation can be handled as an integral part in the floorplanning process. Our method is based on a simulated annealing approach which is divided into two phases: timing optimization phase and buffer insertion phase. Since there is more freedom for floorplan optimization, the floorplanning algorithm integrated with buffer planning can result in better time performance and chip area.

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Cited By

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Dae Hyun Kim Sung Kyu Lim (2015)Physical Design and CAD Tools for 3-D Integrated Circuits: Challenges and OpportunitiesIEEE Design & Test10.1109/MDAT.2015.244031732:4(8-22)Online publication date: Aug-2015
https://doi.org/10.1109/MDAT.2015.2440317
Tang XTian RWong M(2006)Minimizing wire length in floorplanningIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2005.85826625:9(1744-1753)Online publication date: 1-Sep-2006
https://dl.acm.org/doi/10.1109/TCAD.2005.858266
Casu MMacchiarulo L(2006)Throughput-driven floorplanning with wire pipeliningIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2005.84637124:5(663-675)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.2005.846371
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Index Terms

An integrated floorplanning with an efficient buffer planning algorithm
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing

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By dividing the packing area into routing tiles, we can give the budget of the buffer insertion. And the detail locating of the blocks in their rooms can be implemented for each iterations during the annealing process to favor the later buffer planning. ...

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Published In

ISPD '03: Proceedings of the 2003 international symposium on Physical design

April 2003

218 pages

ISBN:1581136501

DOI:10.1145/640000

General Chair:
Massoud Pedram
USC
,
Program Chair:
Charles J. Alpert
IBM

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 06 April 2003

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April 6 - 9, 2003

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Overall Acceptance Rate 62 of 172 submissions, 36%

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Dae Hyun Kim Sung Kyu Lim (2015)Physical Design and CAD Tools for 3-D Integrated Circuits: Challenges and OpportunitiesIEEE Design & Test10.1109/MDAT.2015.244031732:4(8-22)Online publication date: Aug-2015
https://doi.org/10.1109/MDAT.2015.2440317
Tang XTian RWong M(2006)Minimizing wire length in floorplanningIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2005.85826625:9(1744-1753)Online publication date: 1-Sep-2006
https://dl.acm.org/doi/10.1109/TCAD.2005.858266
Casu MMacchiarulo L(2006)Throughput-driven floorplanning with wire pipeliningIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2005.84637124:5(663-675)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.2005.846371
Jahanian AZamani M(2006)Multi-Level Buffer Block Planning and Buffer Insertion for Large Design CircuitsProceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures10.1109/ISVLSI.2006.63Online publication date: 2-Mar-2006
https://dl.acm.org/doi/10.1109/ISVLSI.2006.63
Tang XTian RWong MTang T(2005)Optimal redistribution of white space for wire length minimizationProceedings of the 2005 Asia and South Pacific Design Automation Conference10.1145/1120725.1120900(412-417)Online publication date: 18-Jan-2005
https://dl.acm.org/doi/10.1145/1120725.1120900
Chen SHong XDong SMa YCheng C(2005)Floorplanning with Consideration of White Space Resource Distribution for Repeater PlanningProceedings of the 6th International Symposium on Quality of Electronic Design10.1109/ISQED.2005.58(628-633)Online publication date: 21-Mar-2005
https://dl.acm.org/doi/10.1109/ISQED.2005.58
Bai HDong SHong XChen S(2005)A new buffer planning algorithm based on room resizingProceedings of the 2005 international conference on Embedded and Ubiquitous Computing10.1007/11596356_31(291-299)Online publication date: 6-Dec-2005
https://dl.acm.org/doi/10.1007/11596356_31
Ma YHong XDong SChen SCai YCheng CGu JImai M(2004)Buffer allocation algorithm with consideration of routing congestionProceedings of the 2004 Asia and South Pacific Design Automation Conference10.5555/1015090.1015259(621-623)Online publication date: 27-Jan-2004
https://dl.acm.org/doi/10.5555/1015090.1015259
Casu MMacchiarulo LAlpert, CGroeneveld P(2004)Floorplanning for throughputProceedings of the 2004 international symposium on Physical design10.1145/981066.981081(62-69)Online publication date: 18-Apr-2004
https://dl.acm.org/doi/10.1145/981066.981081
Yuchun Ma Xianiong Hong Sheqin Dong Song Chen Yici Cai Chung-Kuan Cheng Jun Gu (2004)Buffer allocation algorithm with consideration of routing congestionASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)10.1109/ASPDAC.2004.1337666(621-623)Online publication date: 2004
https://doi.org/10.1109/ASPDAC.2004.1337666
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Recommendations

Buffer planning as an Integral part of floorplanning with consideration of routing congestion

Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs

Dynamic global buffer planning optimization based on detail block locating and congestion analysis

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