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Automatic Generation of Micro-kernels for Performance Portability of Matrix Multiplication on RISC-V Vector Processors

Published: 12 November 2023 Publication History

Abstract

In this paper, we propose and evaluate several optimized implementations of the general matrix multiplication (gemm) on two different RISC-V architecture cores implementing the RISC-V vector extension (RVV): C906 and C910 from T-HEAD. Specifically, we address the performance portability problem across these processor cores by means of an automatic assembly code generator, written in Python, capable of emitting RVV code for high performance computing (HPC), with a variety of combinations of specific and general optimizations.
Our experimental results using a number of automatically-generated micro-kernels for gemm, on both RISC-V architectures, reveal different impact of each optimization, depending on the target architecture, and highlight the importance of automatically generating HPC RVV code to achieve performance portability while reducing the developers’ effort. In addition, these optimizations show important performance gains with resepcto to a state-of-the-art tuned BLAS library (OpenBLAS), reaching 3 × and 1.3 × speed-ups for the C910 and C906, respectively.

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MP4 File
Recording of "Automatic Generation of Micro-kernels for Performance Portability of Matrix Multiplication on RISC-V Vector Processors" presentation at the Workshop on RISC-V for HPC 2023.

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cover image ACM Other conferences
SC-W '23: Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis
November 2023
2180 pages
ISBN:9798400707858
DOI:10.1145/3624062
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Published: 12 November 2023

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Author Tags

  1. Automatic code generation
  2. RISC-V ISA
  3. RISC-V vector extension (RVV)
  4. Xuantie C910/C906
  5. matrix multiplication

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