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Multiplexer Optimization for Adders in Stochastic Computing

Authors:

Sercan Aygun,

M. Hassan Najafi,

Lida Kouhalvandi,

Ece Olcay GunesAuthors Info & Claims

NANOARCH '23: Proceedings of the 18th ACM International Symposium on Nanoscale Architectures

Article No.: 18, Pages 1 - 2

https://doi.org/10.1145/3611315.3633256

Published: 25 January 2024 Publication History

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Abstract

This study presents an optimization algorithm for multiplexer (MUX)-based scaled addition for stochastic computing (SC). Accumulation operation can be performed in SC using a MUX unit. Cascaded structures of 2m-to-1 MUXs are used for the accumulation of multiple terms. Optimizing these designs holds significance in cases of accumulating a large number of inputs. The depth of the cascaded MUXs varies with m, affecting the hardware cost, delay, and accuracy. The proposed algorithm performs stage-wise optimization of m. Evaluation results show a lower hardware cost and a higher accuracy compared to the standard MUX-based SC addition using 2-to-1 MUXs for SC-based neural networks.

References

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Sercan Aygun 2021. Efficient and robust bitstream processing in binarised neural networks. El. Lett. 57, 5 (2021), 219–222. https://doi.org/10.1049/ell2.12045

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Brian Gaines. 1969. Stochastic Computing Systems. Springer US, Boston, MA, 37–172. https://doi.org/10.1007/978-1-4899-5841-9_2

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Multiplexer Optimization for Adders in Stochastic Computing
1. Hardware
  1. Emerging technologies

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NANOARCH '23: Proceedings of the 18th ACM International Symposium on Nanoscale Architectures

December 2023

222 pages

ISBN:9798400703256

DOI:10.1145/3611315

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Association for Computing Machinery

New York, NY, United States

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Published: 25 January 2024

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NANOARCH '23

NANOARCH '23: 18th ACM International Symposium on Nanoscale Architectures

December 18 - 20, 2023

Dresden, Germany

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Abstract

References

Index Terms

Recommendations

Scalable Architectures for Design of Reversible Quaternary Multiplexer and Demultiplexer Circuits

Modular Design of testable reversible ALU by QCA multiplexer with increase in programmability

High-performance multiplexer architecture for quantum-dot cellular automata

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