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Power minimization of functional units partially guarded computation

Authors:

Kiyoung ChoiAuthors Info & Claims

ISLPED '00: Proceedings of the 2000 international symposium on Low power electronics and design

Pages 131 - 136

https://doi.org/10.1145/344166.344549

Published: 01 August 2000 Publication History

Abstract

This paper deals with power minimization problem for data-dominated applications based on a novel concept called partially guarded computation. We divide a functional unit into two parts - MSP (Most Significant Part) and LSP (Least Significant Part) - and allow the functional unit to perform only the LSP computation if the range of output data can be covered by LSP. We dynamically disable MSP computation to remove unnecessary transitions thereby reducing power consumption. We also propose a systematic approach for determining optimal location of the boundary between the two parts during high-level synthesis. Experimental results show about 10~44% power reduction with about 30~36% area overhead and less than 3% delay overhead in functional units.

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G VGururaj B(2023)Design of Modified Booth’s Encoder Using SPST techniqueInternational Journal of Electrical Engineering and Computer Science10.37394/232027.2023.5.95(73-86)Online publication date: 18-Jul-2023
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Dutta SBanerjee A(2020)Low Latency and Area Efficient VLSI Architecture of 2D Bilinear Interpolation using Brent Kung Adder Based Fast Multiplier2020 Fourth International Conference on Inventive Systems and Control (ICISC)10.1109/ICISC47916.2020.9171087(673-678)Online publication date: Jan-2020
https://doi.org/10.1109/ICISC47916.2020.9171087
Sahu AKumre L(2017)Low-power less-area bypassing-based multiplier design2017 International Conference on Inventive Computing and Informatics (ICICI)10.1109/ICICI.2017.8365186(522-526)Online publication date: Nov-2017
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Index Terms

Power minimization of functional units partially guarded computation
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
  2. Integrated circuits
    1. Logic circuits

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Published In

cover image ACM Conferences

ISLPED '00: Proceedings of the 2000 international symposium on Low power electronics and design

August 2000

313 pages

ISBN:1581131909

DOI:10.1145/344166

Editors:
David Blaauw
Motorola, Inc., Austin, TX
,
Christian Enz
CSEM, Maladière, Switzerland
,
Thad Gabara
Lucent Technologies
,
Enrico Macii
Politenico di Torino, Turin, Italy

Copyright © 2000 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation
IEEE-CAS: Circuits & Systems

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Association for Computing Machinery

New York, NY, United States

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Published: 01 August 2000

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ISLPED00: International Symposium on Low Power Electronic Design

July 25 - 27, 2000

Rapallo, Italy

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Cited By

G VGururaj B(2023)Design of Modified Booth’s Encoder Using SPST techniqueInternational Journal of Electrical Engineering and Computer Science10.37394/232027.2023.5.95(73-86)Online publication date: 18-Jul-2023
https://doi.org/10.37394/232027.2023.5.9
Dutta SBanerjee A(2020)Low Latency and Area Efficient VLSI Architecture of 2D Bilinear Interpolation using Brent Kung Adder Based Fast Multiplier2020 Fourth International Conference on Inventive Systems and Control (ICISC)10.1109/ICISC47916.2020.9171087(673-678)Online publication date: Jan-2020
https://doi.org/10.1109/ICISC47916.2020.9171087
Sahu AKumre L(2017)Low-power less-area bypassing-based multiplier design2017 International Conference on Inventive Computing and Informatics (ICICI)10.1109/ICICI.2017.8365186(522-526)Online publication date: Nov-2017
https://doi.org/10.1109/ICICI.2017.8365186
Singh SBag SJenamani M(2015)Relative similarity based approach for improving aggregate recommendation diversity2015 Annual IEEE India Conference (INDICON)10.1109/INDICON.2015.7443856(1-6)Online publication date: Dec-2015
https://doi.org/10.1109/INDICON.2015.7443856
Singh KTarunkumar H(2015)A review on various multipliers designs in VLSI2015 Annual IEEE India Conference (INDICON)10.1109/INDICON.2015.7443420(1-4)Online publication date: Dec-2015
https://doi.org/10.1109/INDICON.2015.7443420
ITO KNUMATA T(2013)Valid Digit and Overflow Information to Reduce Energy Dissipation of Functional Units in General Purpose ProcessorsIEICE Transactions on Electronics10.1587/transele.E96.C.463E96.C:4(463-472)Online publication date: 2013
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Seok Won Heo Suk Joong Huh Ercegovac M(2013)Power optimization in a parallel multiplier using voltage islands2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)10.1109/ISCAS.2013.6571851(345-348)Online publication date: May-2013
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Del Barrio AMemik SMolina MMendíAs JHermida R(2013)A fragmentation aware High-Level Synthesis flow for low power heterogenous datapathsIntegration, the VLSI Journal10.1016/j.vlsi.2012.02.00546:2(119-130)Online publication date: 1-Mar-2013
https://dl.acm.org/doi/10.1016/j.vlsi.2012.02.005
Kuang SWu KYu K(2013)Energy-Efficient Multiple-Precision Floating-Point Multiplier for Embedded ApplicationsJournal of Signal Processing Systems10.1007/s11265-012-0695-172:1(43-55)Online publication date: 1-Jul-2013
https://dl.acm.org/doi/10.1007/s11265-012-0695-1
Wang CHsu CSung GLu Y(2012)A Signed Array Multiplier with Bypassing LogicJournal of Signal Processing Systems10.1007/s11265-010-0558-666:2(87-92)Online publication date: 1-Feb-2012
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