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Power consumption reduction in high-speed ΣΔ bandpass modulators

Authors:

P. Cusinato,

F. Stefani,

A. BaschirottoAuthors Info & Claims

ISLPED '00: Proceedings of the 2000 international symposium on Low power electronics and design

Pages 55 - 60

https://doi.org/10.1145/344166.344200

Published: 01 August 2000 Publication History

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Abstract

Power consumption is a key point in the design of high-speed switched capacitor (SC) circuits, which allow to efficiently implement a number of analog functions. Among them, SC ΣΔ modulators are very popular for A/D conversion: in this kind of circuits, operational amplifiers are the most consuming cells because of their requirements in terms of DC gain and unity-gain frequency. A new amplifier with 110dB DC gain and a unity-gain frequency of 250MHz is presented. The large power consumption (20mW) makes critical its use in commercial applications: however, combining this cell with a fast adaptive biasing circuit, high performance may be achieved with a reasonable dissipation.

This approach has been used in the design of a 6th-order bandpass ΣΔ modulator featuring 73dB DR and suitable for the conversion at IF (10.7MHz) of the FM radio signal.

References

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Cusinato PStefani FBaschirotto A(2004)A 6th‐order 75 dB‐DR 10.7 MHz 3.3 V CMOS bandpass ΣΔ modulator sampled at 37.05 MHzInternational Journal of Circuit Theory and Applications10.1002/cta.27732:4(209-222)Online publication date: 22-Jul-2004
https://doi.org/10.1002/cta.277

Index Terms

Power consumption reduction in high-speed ΣΔ bandpass modulators
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
  2. Robustness

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Published In

ISLPED '00: Proceedings of the 2000 international symposium on Low power electronics and design

August 2000

313 pages

ISBN:1581131909

DOI:10.1145/344166

Editors:
David Blaauw
Motorola, Inc., Austin, TX
,
Christian Enz
CSEM, Maladière, Switzerland
,
Thad Gabara
Lucent Technologies
,
Enrico Macii
Politenico di Torino, Turin, Italy

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Association for Computing Machinery

New York, NY, United States

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Published: 01 August 2000

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ISLPED00: International Symposium on Low Power Electronic Design

July 25 - 27, 2000

Rapallo, Italy

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Cusinato PStefani FBaschirotto A(2004)A 6th‐order 75 dB‐DR 10.7 MHz 3.3 V CMOS bandpass ΣΔ modulator sampled at 37.05 MHzInternational Journal of Circuit Theory and Applications10.1002/cta.27732:4(209-222)Online publication date: 22-Jul-2004
https://doi.org/10.1002/cta.277

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A low-power parametric integrator for wideband switched-capacitor ΣΔ modulators

Compact low-power implementation for continuous-time ΣΔ modulators

MASH ΣΔ modulators with a noise-shaped two-step ADC in the second stage

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A low-power parametric integrator for wideband switched-capacitor ΣΔ modulators

Compact low-power implementation for continuous-time ΣΔ modulators

MASH ΣΔ modulators with a noise-shaped two-step ADC in the second stage

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