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Modeling and simulation of real defects using fuzzy logic

Published: 01 June 2000 Publication History

Abstract

Real defects (e.g. stuck-at or bridging faults) in the VLSI circuits cause intermediate voltages and can not be modeled as ideal shorts. In this paper we first show that the traditional zero-resistance model is not sufficient. Then, we present a resistive fault model for real defects and use fuzzy logic techniques for fault simulation and test pattern generation at the gate-level. Our method produces more realistic fault coverage compared to the conventional methods. The experimental results include the fault coverage and test pattern statistics for the ISCAS85 benchmarks.

References

[1]
F. Hawkins, J. Soden, A. Righter and F. Ferguson, "Defect Classes - An Overdue Paradigm for CMOS IC Testing," Proc. Int. Test Conf., pp. 413-425, Oct. 1994.
[2]
R. Aitken, "Finding Defects With Fault Models," Proc. Int. Test Conf., pp. 498-505, Oct. 1995.
[3]
H. Vierhaus, W. Meyer and U. Glaser, "CMOS Bridges and Resistive Transistor Faults IDDQ versus Delay Effects," Proc. Int. Test Conf., pp. 83-91, Oct. 1993.
[4]
N. Weste and K. Eshraghian, Principles of CMOS VLSI Design, Addison-Wesley, 1993.
[5]
Abramovici, M. Breuer and A. Friedman, Digital Systems Testing and Testable Design, Computer Science Press, 1990.
[6]
TI SPICE3 User's and reference manual, 1994 Texas Instrument Incorporation.,
[7]
S. Sparmann, D. Luzenburger, K. Cheng and S. Reddy, "Fast Identification of Robust Dependent Path Delay Faults," Proc. of the 32nd Design Automation Conf., pp. 119-125, June 1995.
[8]
M. Nourani, J. Carletta and C. Papachristou, "A Scheme for Integrated Controller-Datapath Fault Testing," Proc. of the 34th Design Automation Conf., pp. 546-551, June 1997.
[9]
M. Acken and S. Millman, "Fault Model Evolution for Diagnosis: Accuracy vs. Precision," Proc. oflEEE Custom Integrated Circuits Conf., pp. 13.4.1-13.4.4, 1992.
[10]
Chess and T. Larrbee, "Bridge Fault Simulation Strategies for CMOS Integrated Circuits," Proc. of Design Automation Conf., pp. 1503-1507, 1993.
[11]
Di and J. Jess, "An Efficient CMOS Bridging Fault Simulator: with Spice Accuracy," IEEE Trans. on Computer Aided Design, vol. 15, no. 9, pp. 1071-1080, Sept. 1996.
[12]
J. Lee, C. Njinda and M. Breuer, "SWITEST: A Switch Level Test Generation System for CMOS Combinational Circuits," Proc. of Design Automation Conf., pp. 26-29, June 1992.
[13]
Mahlstedt and J. Alt, "Simulation of non-classical Faults on the Gate Level: The Fault Simulator COMSIM," Proc. of Int. Test Conf., pp. 883-892, 1993.
[14]
Rearick and J. Patel, "Fast and Accurate CMOS Bridging Fault Simulation," Proc. oflnt. Test Conf., pp. 54-62, 1993.
[15]
S. Greenstein and J. Patel, "E-PROOFS: A CMOS Bridging Fault Simulator," Proc. of lnt. Conf. Computer Aided Design, 1992.
[16]
X. Wang, A Course in Fuzzy Systems and Control, Prentice-Hall, 1997.
[17]
D. Felthaam and W. Maly, "Physically Realistic Fault Models for Analog CMOS Neural Networks," IEEE Journal of Solid-State Circuits, vol. 26, pp. 1223-1229, Sept. 1991.
[18]
V. Sar-Dessai and D. Walker, "Resistive Bridge Fault Modeling, Simulation and Test Generation," Proc. Int. Test Conf., pp. 596-605, Oct. 1999.
[19]
D. Lavo, B. Chess, T. Larrabee and F. Ferguson, "Diagnosing Realistic Bridging Faults with Single Stuck-at Information," IEEE Trans. on Computer Aided Design, vol. 17, no. 3, March 1998.
[20]
Dalpasso, M. Favalli, P. Olivo and B. Ricco, "Fault Simulation of Parametric Bridging Faults in CMOS IC's," IEEE Trans. on Computer Aided Design, vol. 12, no. 9, pp. 1403-1410, Sept. 1993.
[21]
Jang, C. Sun, and E. Mizutani, Neuro-Fuzzy and Soft Computing, Prentice-Hall, 1997.
[22]
J. Wakerly, Digital Design Principles and Practices, Prentice-Hall, 1990.
[23]
A. Miller, "IDDQ Testing in Deep Submicron Integrated Circuits," Proc. of lnt. Test Conf., pp. 724-729, 1999.
[24]
P. Goel and B. Rosales, "PODEM-X: An Automatic Test Generation System for VLSI Logic Structures," Proc. of Design Automation Conf., pp. 260-268, June 1981.

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cover image ACM Conferences
DAC '00: Proceedings of the 37th Annual Design Automation Conference
June 2000
819 pages
ISBN:1581131879
DOI:10.1145/337292
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 June 2000

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