research-article

DidaSel: dirty data based selection of VC for effective utilization of NVM buffers in on-chip interconnects

Authors:

Sukarn Agarwal,

Hemangee K. KapoorAuthors Info & Claims

ISLPED '20: Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design

Pages 151 - 156

https://doi.org/10.1145/3370748.3406565

Published: 10 August 2020 Publication History

Abstract

In a multi-core system, communication across cores is managed by an on-chip interconnect called Network-on-Chip (NoC). The utilization of NoC results in limitations such as high communication delay and high network power consumption. The buffers of the NoC router consume a considerable amount of leakage power. This paper attempts to reduce leakage power consumption by using Non-Volatile Memory technology-based buffers. NVM technology has the advantage of higher density and low leakage but suffers from costly write operation, and weaker write endurance. These characteristics impact on the total network power consumption, network latency, and lifetime of the router as a whole.

In this paper, we propose a write reduction technique, which is based on dirty flits present in write-back data packets. The method also suggests a dirty flit based Virtual Channel (VC) allocation technique that distributes writes in NVM technology-based VCs to improve the lifetime of NVM buffers.

The experimental evaluation on the full system simulator shows that the proposed policy obtains a 53% reduction in write-back flits, which results in 27% lesser total network flit on average. All these results in a significant decrease in total and dynamic network power consumption. The policy also shows remarkable improvement in the lifetime.

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References

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Cited By

Bhaskar A(2022)A new method of power analysis of Network-on-Chip using analytical modelling2022 Seventh International Conference on Parallel, Distributed and Grid Computing (PDGC)10.1109/PDGC56933.2022.10053136(222-227)Online publication date: 25-Nov-2022
https://doi.org/10.1109/PDGC56933.2022.10053136

Index Terms

DidaSel: dirty data based selection of VC for effective utilization of NVM buffers in on-chip interconnects
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Multicore architectures
2. Hardware
  1. Emerging technologies
    1. Spintronics and magnetic technologies
  2. Integrated circuits
    1. Interconnect

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Published In

cover image ACM Conferences

ISLPED '20: Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design

August 2020

263 pages

ISBN:9781450370530

DOI:10.1145/3370748

Conference Chairs:
David Atienza Alonso
EPFL
,
Qinru Qiu
Syracuse Univ.
,
Program Chairs:
Sherief Reda
Brown Univ.
,
Yiran Chen
Duke Univ.

Copyright © 2020 ACM.

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Published: 10 August 2020

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ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design

August 10 - 12, 2020

Massachusetts, Boston

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Cited By

Bhaskar A(2022)A new method of power analysis of Network-on-Chip using analytical modelling2022 Seventh International Conference on Parallel, Distributed and Grid Computing (PDGC)10.1109/PDGC56933.2022.10053136(222-227)Online publication date: 25-Nov-2022
https://doi.org/10.1109/PDGC56933.2022.10053136

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