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FPGAs in the Datacenter: Combining the Worlds of Hardware and Software Development

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Andrew PutnamAuthors Info & Claims

GLSVLSI '17: Proceedings of the Great Lakes Symposium on VLSI 2017

Page 5

https://doi.org/10.1145/3060403.3066860

Published: 10 May 2017 Publication History

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Abstract

The Catapult project has brought the power and performance of FPGA-based reconfigurable computing to Microsoft's hyperscale datacenters, accelerating major production cloud applications such as Bing web search and Microsoft Azure, and enabling a new generation of machine learning and artificial intelligence applications. Catapult is now deployed in nearly every new server across the more than a million machines that make up the Microsoft hyperscale cloud.

The presence of ubiquitous and programmable silicon in the datacenter ushers in a new era where the discipline and rigor of the VLSI community are combining with the speed and agility of the software community to form new opportunities in a blend development styles and techniques.

In this talk, I will describe the next generation of the Catapult configurable cloud architecture, and the tools and techniques that have made Catapult successful to date. I will also discuss areas where traditional hardware and software development flows fall short, and ways in which the VLSI community can branch into new opportunities in software and computing.

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Del Sozzo EWang XAdhi BCortes CAnderson JSano K(2024)Exploration of Trade-offs Between General-Purpose and Specialized Processing Elements in HPC-Oriented CGRA2024 IEEE International Parallel and Distributed Processing Symposium (IPDPS)10.1109/IPDPS57955.2024.00065(668-680)Online publication date: 27-May-2024
https://doi.org/10.1109/IPDPS57955.2024.00065
Swamy TZulfiqar ANardi LShahbaz MOlukotun KAamodt TJerger NSwift M(2023)Homunculus: Auto-Generating Efficient Data-Plane ML Pipelines for Datacenter NetworksProceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 310.1145/3582016.3582022(329-342)Online publication date: 25-Mar-2023
https://dl.acm.org/doi/10.1145/3582016.3582022
Zhang DHuda SSonghori EPrabhu KLe QGoldie AMirhoseini AFalsafi BFerdman MLu SWenisch T(2022)A full-stack search technique for domain optimized deep learning acceleratorsProceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3503222.3507767(27-42)Online publication date: 28-Feb-2022
https://dl.acm.org/doi/10.1145/3503222.3507767
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FPGAs in the Datacenter: Combining the Worlds of Hardware and Software Development

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Published In

GLSVLSI '17: Proceedings of the Great Lakes Symposium on VLSI 2017

May 2017

516 pages

ISBN:9781450349727

DOI:10.1145/3060403

General Chairs:
Laleh Behjat
University of Calgary, Canada
,
Jie Han
University of Alberta, Canada
,
Program Chairs:
Miroslav N. Velev
Aries Design Automation, USA
,
Deming Chen
University of Illinois, USA

Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 10 May 2017

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GLSVLSI '17

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SIGDA

GLSVLSI '17: Great Lakes Symposium on VLSI 2017

May 10 - 12, 2017

Alberta, Banff, Canada

Acceptance Rates

GLSVLSI '17 Paper Acceptance Rate 48 of 197 submissions, 24%;

Overall Acceptance Rate 312 of 1,156 submissions, 27%

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GLSVLSI '25

Sponsor:
sigda

Great Lakes Symposium on VLSI 2025

June 30 - July 2, 2025

New Orleans , LA , USA

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Del Sozzo EWang XAdhi BCortes CAnderson JSano K(2024)Exploration of Trade-offs Between General-Purpose and Specialized Processing Elements in HPC-Oriented CGRA2024 IEEE International Parallel and Distributed Processing Symposium (IPDPS)10.1109/IPDPS57955.2024.00065(668-680)Online publication date: 27-May-2024
https://doi.org/10.1109/IPDPS57955.2024.00065
Swamy TZulfiqar ANardi LShahbaz MOlukotun KAamodt TJerger NSwift M(2023)Homunculus: Auto-Generating Efficient Data-Plane ML Pipelines for Datacenter NetworksProceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 310.1145/3582016.3582022(329-342)Online publication date: 25-Mar-2023
https://dl.acm.org/doi/10.1145/3582016.3582022
Zhang DHuda SSonghori EPrabhu KLe QGoldie AMirhoseini AFalsafi BFerdman MLu SWenisch T(2022)A full-stack search technique for domain optimized deep learning acceleratorsProceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3503222.3507767(27-42)Online publication date: 28-Feb-2022
https://dl.acm.org/doi/10.1145/3503222.3507767
Vu HTran DBui NLe TNguyen H(2022)Mapping Boolean Functions onto Lookup-Tables on FPGAs2022 RIVF International Conference on Computing and Communication Technologies (RIVF)10.1109/RIVF55975.2022.10013797(508-512)Online publication date: 20-Dec-2022
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Zhang LYan XMa D(2022)A Binarized Neural Network Approach to Accelerate in-Vehicle Network Intrusion DetectionIEEE Access10.1109/ACCESS.2022.320809110(123505-123520)Online publication date: 2022
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Zhou TPan TMeyer MDong YWatanabe T(2020)Multi-Shape Task Placement Algorithm Based on Low Fragmentation Resource Management on 2D Heterogeneous Dynamic Partial Reconfigurable DevicesIEEE Access10.1109/ACCESS.2020.30298388(186362-186375)Online publication date: 2020
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Khairy MWassal AZahran M(2019)A survey of architectural approaches for improving GPGPU performance, programmability and heterogeneityJournal of Parallel and Distributed Computing10.1016/j.jpdc.2018.11.012127:C(65-88)Online publication date: 1-May-2019
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Margerm SSharifian AGuha AShriraman APokam GOskin MInoue K(2018)TAPASProceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2018.00028(245-257)Online publication date: 20-Oct-2018
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Vu HNakada TNakashima Y(2018)Efficient Multitasking on FPGA Using HDL-Based CheckpointingApplied Reconfigurable Computing. Architectures, Tools, and Applications10.1007/978-3-319-78890-6_47(590-602)Online publication date: 8-Apr-2018
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Plugariu OGegiu APetrica L(2017)FPGA systolic array GZIP compressor2017 9th International Conference on Electronics, Computers and Artificial Intelligence (ECAI)10.1109/ECAI.2017.8166387(1-6)Online publication date: Jun-2017
https://doi.org/10.1109/ECAI.2017.8166387

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FPGAs and Their Evolving Role in Domain Specific Architectures: A Case Study of the AMD 400G Adaptive SmartNIC/DPU SoC

HyperParser: A High-Performance Parser Architecture for Next Generation Programmable Switch and SmartNIC

FPGAs in the Datacenter: Enhancing Performance, Usability, Security, and Privacy

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