research-article

VWS: a versatile warp scheduler for exploring diverse cache localities of GPGPU applications

Authors:

Hai LiAuthors Info & Claims

DAC '15: Proceedings of the 52nd Annual Design Automation Conference

Article No.: 83, Pages 1 - 6

https://doi.org/10.1145/2744769.2744931

Published: 07 June 2015 Publication History

Abstract

Massive multi-threading of GPGPU demands for efficient usage of caches with limited capacity. In this work, we propose a versatile warp scheduler (VWS) to reduce the cache miss rate in GPGPU. VWS retains the intra-warp cache locality using an efficient per-warp working set estimator and enhances intra-/inter-cooperative thread array (CTA) cache locality through imposing a CTA-aware scheduling policy and a new CTA dispatching mechanism. The significantly improved hit rate of cache hierarchy enables VWS to achieve on average 38.4% and 9.3% IPC improvement across diverse GPGPU applications compared to a widely-used and a state-of-the-art warp schedulers, respectively.

References

[1]

"Amd graphics core next (gcn) architecture." http://www.amd.com/en-gb/innovations/software-technologies/gcn/.

[2]

"Nvidia cuda c programming guide." https://docs.nvidia.com/cuda/cuda-c-programming-guide/.

[3]

"Nvidia fermi architecture." http://www.nvidia.com/object/fermi-architecture.html/.

[4]

"Nvidia maxwell architecture." https://developer.nvidia.com/maxwell-compute-architecture/.

[5]

"Opencl." https://www.khronos.org/opencl/.

[6]

A. Bakhoda et al., "Analyzing cuda workloads using a detailed gpu simulator," in ISPASS, 2009, pp. 163--174.

[7]

S. Che et al., "Rodinia: A benchmark suite for heterogeneous computing," in IISWC, 2009, pp. 44--54.

Digital Library

[8]

J. Fix, A. Wilkes, and K. Skadron, "Accelerating braided b+ tree searches on a gpu with cuda," in A4MMC, 2011.

[9]

M. Gebhart et al., "Energy-efficient mechanisms for managing thread context in throughput processors," in ISCA, 2011, pp. 235--246.

Digital Library

[10]

B. He et al., "Mars: a mapreduce framework on graphics processors," in PACT, 2008, pp. 260--269.

Digital Library

[11]

A. Jaleel et al., "High performance cache replacement using re-reference interval prediction (rrip)," in ACM SIGARCH Computer Architecture News, vol. 38, no. 3, 2010, pp. 60--71.

Digital Library

[12]

W. Jia, K. A. Shaw, and M. Martonosi, "Characterizing and improving the use of demand-fetched caches in gpus," in ICS, 2012, pp. 15--24.

Digital Library

[13]

A. Jog et al., "Owl: cooperative thread array aware scheduling techniques for improving gpgpu performance," in ASPLOS, 2013, pp. 395--406.

Digital Library

[14]

M. Lee et al., "Improving gpgpu resource utilization through alternative thread block scheduling," in HPCA, 2014, pp. 260--271.

[15]

T. G. Rogers, M. O'Connor, and T. M. Aamodt, "Cache-conscious wavefront scheduling," in MICRO, 2012, pp. 72--83.

Digital Library

[16]

T. G. Rogers, M. O'Connor, and T. M. Aamodt, "Divergence-aware warp scheduling," in MICRO, 2013, pp. 99--110.

Digital Library

[17]

J. A. Stratton et al., "Parboil: A revised benchmark suite for scientific and commercial throughput computing," Center for Reliable and High-Performance Computing, 2012.

Cited By

Shoushtary MArnau JMurgadas JGonzalez A(2024)Memento: An Adaptive, Compiler-Assisted Register File Cache for GPUs2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA)10.1109/ISCA59077.2024.00075(978-990)Online publication date: 29-Jun-2024
https://doi.org/10.1109/ISCA59077.2024.00075
Oh YKoo GAnnavaram MRo WManne SHunter HAltman E(2019)LinebackerProceedings of the 46th International Symposium on Computer Architecture10.1145/3307650.3322222(183-196)Online publication date: 22-Jun-2019
https://dl.acm.org/doi/10.1145/3307650.3322222
Wang LZhao XKaeli DWang ZEeckhout L(2019)Intra-Cluster Coalescing and Distributed-Block Scheduling to Reduce GPU NoC PressureIEEE Transactions on Computers10.1109/TC.2019.289503668:7(1064-1076)Online publication date: 1-Jul-2019
https://doi.org/10.1109/TC.2019.2895036
Show More Cited By

Index Terms

VWS: a versatile warp scheduler for exploring diverse cache localities of GPGPU applications
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Multiple instruction, multiple data

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cover image ACM Conferences

DAC '15: Proceedings of the 52nd Annual Design Automation Conference

June 2015

1204 pages

ISBN:9781450335201

DOI:10.1145/2744769

Copyright © 2015 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Published: 07 June 2015

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DAC '15: The 52nd Annual Design Automation Conference 2015

June 7 - 11, 2015

California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Shoushtary MArnau JMurgadas JGonzalez A(2024)Memento: An Adaptive, Compiler-Assisted Register File Cache for GPUs2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA)10.1109/ISCA59077.2024.00075(978-990)Online publication date: 29-Jun-2024
https://doi.org/10.1109/ISCA59077.2024.00075
Oh YKoo GAnnavaram MRo WManne SHunter HAltman E(2019)LinebackerProceedings of the 46th International Symposium on Computer Architecture10.1145/3307650.3322222(183-196)Online publication date: 22-Jun-2019
https://dl.acm.org/doi/10.1145/3307650.3322222
Wang LZhao XKaeli DWang ZEeckhout L(2019)Intra-Cluster Coalescing and Distributed-Block Scheduling to Reduce GPU NoC PressureIEEE Transactions on Computers10.1109/TC.2019.289503668:7(1064-1076)Online publication date: 1-Jul-2019
https://doi.org/10.1109/TC.2019.2895036
Wang LZhao XKaeli DWang ZEeckhout L(2018)Intra-Cluster Coalescing to Reduce GPU NoC Pressure2018 IEEE International Parallel and Distributed Processing Symposium (IPDPS)10.1109/IPDPS.2018.00108(990-999)Online publication date: May-2018
https://doi.org/10.1109/IPDPS.2018.00108
Mao MWen WLiu XHu JWang DChen YLi H(2016)TEMPProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2898103(1-6)Online publication date: 5-Jun-2016
https://dl.acm.org/doi/10.1145/2897937.2898103

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