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Designing high performance CMOS microprocessors using full custom techniques

Authors:

William J. Grundmann,

Dan Dobberpuhl,

Randy L. Allmon,

Nicholas L. RethmanAuthors Info & Claims

DAC '97: Proceedings of the 34th annual Design Automation Conference

Pages 722 - 727

https://doi.org/10.1145/266021.266353

Published: 13 June 1997 Publication History

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Abstract

In this paper, we describe a full customCMOS design methodology and supporting CADtechnologies used to develop ALPHA and StrongARMmicroprocessors at Digital Semiconductor. The paper issubdivided into four parts, starting with a description ofthe design methodology and general CAD flows.Additional sections focus on two particular areas ofinterest: high performance low-power and full customdesign benefits and verification issues.

References

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D. Dobberpuhl, et. al., "A 200MHz 64b Dual-Issue CMOS Microprocessor," IEEE Journal of Solid State Circuits, vol. 27, no. 11, Nov., 1992.

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P. Gronowski, et. al., "A 433Mhz 64b Quad-Issue CMOS RISC Microprocessor," ISSCC Digest of Technical Papers, pp. 222-223, Feb., 1996.

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B. Gieseke, et. al., "A 600mhz Superscalar RISC Microprocessor With Out-of-Order Execution," ISSCC Digest of Technical Papers, pp. 176-177, Feb., 1997.

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P. Gronowski, et. al., "A 433 MHz 64b Quad-Issue RISC Microprocessor", IEEE Journal of Solid State Circuits, vol. 31, no 11, page 1687-1696, Nov., 1996.

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Cited By

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Song HBohidar SBahar RGrodstein J(2003)Symbolic failure analysis of custom circuits due to excessive leakage currentProceedings 21st International Conference on Computer Design10.1109/ICCD.2003.1240875(70-75)Online publication date: 2003
https://doi.org/10.1109/ICCD.2003.1240875
Kawakami YFang JYonezawa HIwanishi NWu LChen AKoike NChen PYeh CLiu ZYoshida K(2000)Gate-level aged timing simulation methodology for hot-carrier reliability assuranceProceedings of the 2000 Asia and South Pacific Design Automation Conference10.1145/368434.368636(289-294)Online publication date: 28-Jan-2000
https://dl.acm.org/doi/10.1145/368434.368636
Kirkpatrick DWong D(1999)The deep sub-micron signal integrity challengeProceedings of the 1999 international symposium on Physical design10.1145/299996.300005(4-7)Online publication date: 12-Apr-1999
https://dl.acm.org/doi/10.1145/299996.300005
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Designing high performance CMOS microprocessors using full custom techniques

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Published In

DAC '97: Proceedings of the 34th annual Design Automation Conference

June 1997

788 pages

ISBN:0897919203

DOI:10.1145/266021

Chairmen:
Ellen J. Yoffa
IBM T. J. Watson Research Center, Yorktown Heights, NY
,
Giovanni De Micheli
Stanford Univ., Stanford, CA
,
Jan M. Rabaey
Univ. of California, Berkeley

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 13 June 1997

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DAC97: The 34th Design Automation Conference

June 9 - 13, 1997

California, Anaheim, USA

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DAC '97 Paper Acceptance Rate 139 of 400 submissions, 35%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Song HBohidar SBahar RGrodstein J(2003)Symbolic failure analysis of custom circuits due to excessive leakage currentProceedings 21st International Conference on Computer Design10.1109/ICCD.2003.1240875(70-75)Online publication date: 2003
https://doi.org/10.1109/ICCD.2003.1240875
Kawakami YFang JYonezawa HIwanishi NWu LChen AKoike NChen PYeh CLiu ZYoshida K(2000)Gate-level aged timing simulation methodology for hot-carrier reliability assuranceProceedings of the 2000 Asia and South Pacific Design Automation Conference10.1145/368434.368636(289-294)Online publication date: 28-Jan-2000
https://dl.acm.org/doi/10.1145/368434.368636
Kirkpatrick DWong D(1999)The deep sub-micron signal integrity challengeProceedings of the 1999 international symposium on Physical design10.1145/299996.300005(4-7)Online publication date: 12-Apr-1999
https://dl.acm.org/doi/10.1145/299996.300005
Gowan MBiro LJackson DChawla BBryant RRabaey J(1998)Power considerations in the design of the Alpha 21264 microprocessorProceedings of the 35th annual Design Automation Conference10.1145/277044.277226(726-731)Online publication date: 1-May-1998
https://dl.acm.org/doi/10.1145/277044.277226
Nassif NDesai MHall DChawla BBryant RRabaey J(1998)Robust Elmore delay models suitable for full chip timing verification of a 600MHz CMOS microprocessorProceedings of the 35th annual Design Automation Conference10.1145/277044.277104(230-235)Online publication date: 1-May-1998
https://dl.acm.org/doi/10.1145/277044.277104

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High Performance CMOS Transconductor for Mixed-Signal Analog-Digital Applications

Hardware-Oriented Krylov Methods for High-Performance Computing

Design of a novel CMOS Gilbert mixer with high performance

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High Performance CMOS Transconductor for Mixed-Signal Analog-Digital Applications

Hardware-Oriented Krylov Methods for High-Performance Computing

Design of a novel CMOS Gilbert mixer with high performance

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