Co-optimization of TSV assignment and micro-channel placement for 3D-ICs

The three dimensional circuit (3D-IC) brings forth new challenges to physical design such as allocation and management of through-silicon-vias (TSVs). Meanwhile, the thermal issues in 3D-IC becomes significant necessitating the use of active cooling schemes such as micro-channel liquid coolings. Both TSVs and micro-channels go through the interlayer regions of 3D-IC resulting in potential resource conflict. This paper investigates the co-optimization of TSV assignment to interlayer nets and micro-channel allocation such that both wirelength and micro-channel cooling energy are co-optimized. We propose a multi-commodity flow based formulation to solve the co-optimization. The experimental results show that, our approach achieves 51% cooling power savings or 6.08% wire length reduction compared with the approaches that assign TSVs and allocate micro-channels separately.