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Layout driven logic synthesis for FPGAs

Authors:

Shih-Chieh Chang,

Kwang-Ting Cheng,

Nam-Sung Woo,

Malgorzata Marek-SadowskaAuthors Info & Claims

DAC '94: Proceedings of the 31st annual Design Automation Conference

Pages 308 - 313

https://doi.org/10.1145/196244.196388

Published: 06 June 1994 Publication History

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References

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Shih-Chieh. Chang and Malgorzata Marek-Sadowska, "Technology Mapping via Transformations of Function Graphs", Proc. IEEE International Conference on Computer Design, pp. 159-162, 1992.

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R.J.Francis, J.Rose and Z.Vranesic, "Chortle-crf: Fast Technology Mapping for Lookup Table-Based FPGAs", Proc. 28th Design Automation Conf., pp. 227-233, June 1991.

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Cited By

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Gunter AWilton S(2023)A Machine Learning Approach for Predicting the Difficulty of FPGA Routing Problems2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM57271.2023.00016(63-74)Online publication date: May-2023
https://doi.org/10.1109/FCCM57271.2023.00016
Boland DCheng CKahng ALeong P(2017)Reconfigurable ComputingWiley Encyclopedia of Electrical and Electronics Engineering10.1002/047134608X.W7603.pub3(1-17)Online publication date: 15-Feb-2017
https://doi.org/10.1002/047134608X.W7603.pub3
Lam TTang WYang XWu Y(2012)ECRACM Transactions on Design Automation of Electronic Systems10.1145/2348839.234885417:4(1-21)Online publication date: 1-Oct-2012
https://dl.acm.org/doi/10.1145/2348839.2348854
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Index Terms

Layout driven logic synthesis for FPGAs
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
    2. Physical design (EDA)
      1. Partitioning and floorplanning
  2. Very large scale integration design
    1. Application-specific VLSI designs

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DAC '94: Proceedings of the 31st annual Design Automation Conference

June 1994

739 pages

ISBN:0897916530

DOI:10.1145/196244

Chairman:
Michael Lorenzetti
Mentor Graphics Corp., Wilsonville, OR

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 06 June 1994

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DAC94: The 31st ACM/IEEE-CAS/EDAC Design Automation Conference

June 6 - 10, 1994

California, San Diego, USA

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DAC '94 Paper Acceptance Rate 100 of 260 submissions, 38%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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DAC '25

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62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

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Gunter AWilton S(2023)A Machine Learning Approach for Predicting the Difficulty of FPGA Routing Problems2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM57271.2023.00016(63-74)Online publication date: May-2023
https://doi.org/10.1109/FCCM57271.2023.00016
Boland DCheng CKahng ALeong P(2017)Reconfigurable ComputingWiley Encyclopedia of Electrical and Electronics Engineering10.1002/047134608X.W7603.pub3(1-17)Online publication date: 15-Feb-2017
https://doi.org/10.1002/047134608X.W7603.pub3
Lam TTang WYang XWu Y(2012)ECRACM Transactions on Design Automation of Electronic Systems10.1145/2348839.234885417:4(1-21)Online publication date: 1-Oct-2012
https://dl.acm.org/doi/10.1145/2348839.2348854
CHIM FLAM TWU YFAN H(2011)On Structural Analysis and Efficiency for Graph-Based Rewiring TechniquesIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E94.A.2853E94-A:12(2853-2865)Online publication date: 2011
https://doi.org/10.1587/transfun.E94.A.2853
Yang XLam TWu YSapatnekar S(2010)ECRProceedings of the 47th Design Automation Conference10.1145/1837274.1837400(511-516)Online publication date: 13-Jun-2010
https://dl.acm.org/doi/10.1145/1837274.1837400
Yang XXiao ZWu Y(2010)Improving redundancy addition and removal using unreachable states for sequential circuitsProceedings of 2010 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2010.5537956(3172-3175)Online publication date: May-2010
https://doi.org/10.1109/ISCAS.2010.5537956
Wu CLin THuang SHuang CWakabayashi K(2009)SAT-controlled redundancy addition and removalProceedings of the 2009 Asia and South Pacific Design Automation Conference10.5555/1509633.1509691(191-196)Online publication date: 19-Jan-2009
https://dl.acm.org/doi/10.5555/1509633.1509691
Xiaoqing Yang Wu Y(2009)Fast logic restructuring exploring fanout-reconvergent structures and extended symmetry detections2009 International Conference on Communications, Circuits and Systems10.1109/ICCCAS.2009.5250321(1113-1118)Online publication date: Jul-2009
https://doi.org/10.1109/ICCCAS.2009.5250321
Chung‐Kuan CKahng ALeong P(2007)Reconfigurable ComputingWiley Encyclopedia of Electrical and Electronics Engineering10.1002/047134608X.W7603.pub2Online publication date: 15-Jun-2007
https://doi.org/10.1002/047134608X.W7603.pub2
Khatri SSinha SBrayton RSangiovanni-Vincentelli A(2006)SPFD-based wire removal in standard-cell and network-of-PLA circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2004.82982123:7(1020-1030)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.2004.829821
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Layout-driven RTL binding techniques for high-level synthesis

Integration of behavioral and layout synthesis: a chip synthesis approach

Optimized hardware synthesis for fpgas

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Layout-driven RTL binding techniques for high-level synthesis

Integration of behavioral and layout synthesis: a chip synthesis approach

Optimized hardware synthesis for fpgas

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