research-article

Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing

Authors:

Tolga SoyataAuthors Info & Claims

ISCA '10: Proceedings of the 37th annual international symposium on Computer architecture

Pages 371 - 382

https://doi.org/10.1145/1815961.1816012

Published: 19 June 2010 Publication History

Abstract

As CMOS scales beyond the 45nm technology node, leakage concerns are starting to limit microprocessor performance growth. To keep dynamic power constant across process generations, traditional MOSFET scaling theory prescribes reducing supply and threshold voltages in proportion to device dimensions, a practice that induces an exponential increase in subthreshold leakage. As a result, leakage power has become comparable to dynamic power in current-generation processes, and will soon exceed it in magnitude if voltages are scaled down any further. Beyond this inflection point, multicore processors will not be able to afford keeping more than a small fraction of all cores active at any given moment. Multicore scaling will soon hit a power wall.

This paper presents resistive computation, a new technique that aims at avoiding the power wall by migrating most of the functionality of a modern microprocessor from CMOS to spin-torque transfer magnetoresistive RAM (STT-MRAM)---a CMOS-compatible, leakage-resistant, non-volatile resistive memory technology. By implementing much of the on-chip storage and combinational logic using leakage-resistant, scalable RAM blocks and lookup tables, and by carefully re-architecting the pipeline, an STT-MRAM based implementation of an eight-core Sun Niagara-like CMT processor reduces chip-wide power dissipation by 1.7× and leakage power by 2.1× at the 32nm technology node, while maintaining 93% of the system throughput of a CMOS-based design.

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Index Terms

Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
2. Hardware
  1. Integrated circuits
    1. Semiconductor memory

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cover image ACM Conferences

ISCA '10: Proceedings of the 37th annual international symposium on Computer architecture

June 2010

520 pages

ISBN:9781450300537

DOI:10.1145/1815961

General Chair:
André Seznec
INRIA Rennes
,
Program Chairs:
Uri Weiser
Technion
,
Ronny Ronen
Intel

ACM SIGARCH Computer Architecture News Volume 38, Issue 3
ISCA '10
June 2010
508 pages
ISSN:0163-5964
DOI:10.1145/1816038
Issue’s Table of Contents

Copyright © 2010 ACM.

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Published: 19 June 2010

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June 19 - 23, 2010

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https://doi.org/10.1109/ACCESS.2023.3327261
Benson LPapke LRabl T(2022)PerMA-benchProceedings of the VLDB Endowment10.14778/3551793.355180715:11(2463-2476)Online publication date: 29-Sep-2022
https://dl.acm.org/doi/10.14778/3551793.3551807
Han HAlexoudi TVagionas CPleros NHardavellas N(2022)A Practical Shared Optical Cache With Hybrid MWSR/R-SWMR NoC for Multicore ProcessorsACM Journal on Emerging Technologies in Computing Systems10.1145/353101218:4(1-28)Online publication date: 13-Oct-2022
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