research-article

A high-level clustering algorithm targeting dual V_dd FPGAs

Authors:

Rajarshi Mukherjee,

Seda Ogrenci Memik,

Somsubhra MondalAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 13, Issue 4

Article No.: 57, Pages 1 - 20

https://doi.org/10.1145/1391962.1391965

Published: 03 October 2008 Publication History

Abstract

Recent advanced power optimizations deployed in commercial FPGAs, laid out a roadmap towards FPGA devices that can be integrated into ultra low power systems. In this article, we present a high-level design tool to support the process of mapping an application onto a FPGA device with dual supply voltages. Our main contribution in this paper is an algorithm, which creates voltage scaling ready clusters by utilizing the timing slack available in the designs. We propose to first create clusters of CLBs within a given CLB-level netlist. This clustering algorithm intends to group chains of CLBs possessing similar amounts of timing slack along their critical path together. Once these clusters are identified, they are placed onto respective V_dd partitions on the device. We have evaluated different dual V_dd fabrics and the potential gain in power consumption is explored. When a subset of the logic blocks on the device can be driven by low V_dd levels (either with a dedicated low V_dd supply or with a programmable selection between low and high V_dd levels for these blocks) this affects placement and routing. As a result the maximum frequency of the designs may be affected. In order to evaluate the overall impact of creating voltage islands, we measured the Energy-Delay Product for our benchmark designs. We observed that the Energy-Delay product can be decreased by 26.9% when the placement of the designs into different voltage levels is guided by our clustering algorithm.

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Cited By

Joshi SLi DOgrenci-Memik SDeptuch GHoff JJindariani SLiu TOlsen JTran N(2018)Multi-Vdd Design for Content Addressable Memories (CAM): A Power-Delay Optimization AnalysisJournal of Low Power Electronics and Applications10.3390/jlpea80300258:3(25)Online publication date: 30-Jul-2018
https://doi.org/10.3390/jlpea8030025

Index Terms

A high-level clustering algorithm targeting dual V_dd FPGAs
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 13, Issue 4

September 2008

328 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/1391962

Issue’s Table of Contents

Copyright © 2008 ACM.

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Association for Computing Machinery

New York, NY, United States

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 03 October 2008

Accepted: 01 May 2008

Revised: 01 July 2007

Received: 01 May 2007

Published in TODAES Volume 13, Issue 4

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Cited By

Joshi SLi DOgrenci-Memik SDeptuch GHoff JJindariani SLiu TOlsen JTran N(2018)Multi-Vdd Design for Content Addressable Memories (CAM): A Power-Delay Optimization AnalysisJournal of Low Power Electronics and Applications10.3390/jlpea80300258:3(25)Online publication date: 30-Jul-2018
https://doi.org/10.3390/jlpea8030025

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