Thirty-four undergraduates implemented a MIPS R2000 processor for an introductory CMOS VLSI design course. This included designing a microarchitecture in Verilog, developing custom PLA generation and ad-hoc random testing tools, creating a standard cell library, schematics, layout, and PCB test board. The processor was fabricated by MOSIS on an AMI 0.5-micron process, included 160,000 transistors, and ran at 7.25 MHz.

References

[1]

M. Horowitz, et. al., "MIPS-X: a 20-MIPS peak, 32-bit microprocessor," IEEE Journal of Solid-State Circuits, vol. 22, no. 5, pp. 790--799, Oct. 1987.

Crossref

Google Scholar

[2]

D. Sweetman, See MIPS Run, San Diego: Academic Press, 2002.

Digital Library

Google Scholar

[3]

"Google Code hmc-mips," http://code.google.com/p/hmc-mips/

Google Scholar

[4]

"E158 CMOS VLSI Design Spring 2007 MIPS Project," http://www4.hmc.edu:8001/Engineering/158/07/project/

Google Scholar

[5]

A. Weiss, "Dhrystone Benchmark: History, Analysis, 'Scores,' and Recommendations White Paper," Nov. 2002, http://www.synchromeshcomputing.com/pdf/dhrystoneWhitePaper.pdf

Google Scholar

[6]

D. Grevenstein, "Dhyrstone Benchmark Results," http://sites.inka.de/pcde/dbp/dhrystone.html

Google Scholar

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Waugaman MDavidson ZDietrich SJohnson DMeyer CStorm EThaker AWong I(2016)LEG processor for education2016 11th European Workshop on Microelectronics Education (EWME)10.1109/EWME.2016.7496467(1-5)Online publication date: May-2016
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Casu MMantovani P(2015)A synchronous latency-insensitive RISC for better than worst-case designIntegration, the VLSI Journal10.1016/j.vlsi.2014.01.00348:C(72-82)Online publication date: 1-Jan-2015
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Quinn HBlack DRobinson WBuchner S(2013)Fault Simulation and Emulation Tools to Augment Radiation-Hardness Assurance TestingIEEE Transactions on Nuclear Science10.1109/TNS.2013.225950360:3(2119-2142)Online publication date: Jun-2013
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Index Terms

A MIPS R2000 implementation
1. Applied computing
  1. Computers in other domains
    1. Personal computers and PC applications
      1. Microcomputers

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DAC '08: Proceedings of the 45th annual Design Automation Conference

June 2008

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DOI:10.1145/1391469

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Intel Research Pittsburgh, Pittsburgh, PA

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