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ESL design and HW/SW co-verification of high-end software defined radio platforms

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L. Van der PerreAuthors Info & Claims

CODES+ISSS '07: Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis

Pages 191 - 196

https://doi.org/10.1145/1289816.1289864

Published: 30 September 2007 Publication History

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Abstract

Multiple wireless technologies are converging to run on personal handhelds. The plethora of communication standards next to the cost issues of deeper submicron processing require handheld platforms to shift from sets of multiple application specific ICs (ASICs) to multi-purpose Multi-Processor System-on-Chip (MPSoC) on which Software Defined Radios (SDR) are run. SDR design faces hard real-time processing and data transfer latency constraints. Designing SDR under stringent time-to-market (cost), energy and real-time processing constraints requires the help of advanced Electronic System-Level (ESL) design methodologies. This paper demonstrates an integrated ESL design flow built on advanced ESL tools to design SDR platforms for handhelds. We share the experience from creation of a high-level virtual platform model down to hardware/software (HW/SW) co-verification of a large scale SoC (5 million gates+). Incremental RTL verification based on co-simulation and co-emulation is also presented.

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Cited By

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Kyuho Shim Woojoo Kim Kwang-Hyun Cho Byeong Min (2012)System-level simulation acceleration for architectural performance analysis using hybrid virtual platform system2012 International SoC Design Conference (ISOCC)10.1109/ISOCC.2012.6407126(402-404)Online publication date: Nov-2012
https://doi.org/10.1109/ISOCC.2012.6407126

Index Terms

ESL design and HW/SW co-verification of high-end software defined radio platforms
1. Hardware
  1. Hardware validation

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Published In

CODES+ISSS '07: Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis

September 2007

284 pages

ISBN:9781595938244

DOI:10.1145/1289816

General Chairs:
Soonhoi Ha
Seoul National University, Korea
,
Kiyoung Choi
Seoul National University, Korea
,
Program Chairs:
Nikil Dutt
UC Irvine, USA
,
Jürgen Teich
University of Erlangen-Nuremberg, Germany

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 30 September 2007

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ESWEEK07

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ESWEEK07: Third Embedded Systems Week

September 30 - October 3, 2007

Salzburg, Austria

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Overall Acceptance Rate 280 of 864 submissions, 32%

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Kyuho Shim Woojoo Kim Kwang-Hyun Cho Byeong Min (2012)System-level simulation acceleration for architectural performance analysis using hybrid virtual platform system2012 International SoC Design Conference (ISOCC)10.1109/ISOCC.2012.6407126(402-404)Online publication date: Nov-2012
https://doi.org/10.1109/ISOCC.2012.6407126

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A hardware/software co-design approach to prototype 6G mobile applications inside the GNU Radio SDR Ecosystem using FPGA hardware accelerators

High-Throughput, Low-Power Software-Defined Radio Using Reconfigurable Processors

Domain-Specific Language for HW/SW Co-design for FPGAs