Article

Coupling EA and high-level metrics for the automatic generation of test blocks for peripheral cores

Authors:

Leticia Bolzani,

Ernesto Sanchez,

Massimiliano Schillaci,

Giovanni SquilleroAuthors Info & Claims

GECCO '07: Proceedings of the 9th annual conference on Genetic and evolutionary computation

Pages 1912 - 1919

https://doi.org/10.1145/1276958.1277342

Published: 07 July 2007 Publication History

Abstract

Test of peripheral modules has not been deeply investigated by the research community. When embedded in a system on chip, however, peripherals pose accessibility problems that may make traditional test approaches ineffective. In this paper an evolutionary methodology, based upon coverage metrics at high-level, is described to automatically generate test sets for peripheral modules in a SoC. A general-purpose evolutionary tool, able to cultivate composite individuals, has been developed and isused for the test set generation. This tool is described and its basic concepts explained. The method compares favorably with results obtained by hand.

References

[1]

N. Kranitis, A. Paschalis, D. Gizopoulos, G. Xenoulis, "Software-based self-testing of embedded processors", IEEE Transactions on Computers, Vol 54, issue 4, pp 461 -- 475, April 2005.

Digital Library

[2]

A. Manzone, P. Bernardi, M. Grosso, M. Rebaudengo, E. Sanchez, M. Sonza Reorda, "Integrating BIST techniques for on-line SoC testing," IOLTS 2005: IEEE International Online Testing Symposium, 2005, pp. 235--240

Digital Library

[3]

S.Thatte, J.Abraham, "Test Generation for Microprocessors", IEEE Transactions on Computers, Vol. C-29, pp 429--441, 1980

[4]

C.A. Papachristou, F. Martin, M. Nourani, "Microprocessor Based Testing for Core-Based System on Chip", ACM/IEEE Design Automation Conference, pp 586--591, 1999

Digital Library

[5]

F. Corno, M. Sonza Reorda, G. Squillero, M. Violante, "On the Test of Microprocessor IP Cores", IEEE Design, Automation & Test in Europe, pp 209--213, 2001

Digital Library

[6]

A. Cheng, A. Parashkevov, and C.C. Lim, "A Software Test Program Generator for Verifying System-on-Chip", 10th IEEE International High Level Design Validation and Test Workshop 2005 (HLDVT'05), Napa Valley, California USA: IEEE Computer, 2005, pp. 79--86

Digital Library

[7]

F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero, "An RT-level Fault Model with High Gate Level Correlation", HLDVT2000: IEEE International High Level Design Validation and Test Workshop, The Claremont Resort & Spa, Berkeley, California, November 8--10 2000

Digital Library

[8]

P. C. Maxwell, R. C. Aitken, V. Johansen, I. Chiang, "The effect of different test sets on quality level prediction: When is 80% better than 90%?", IEEE proc. of the International Test Conference, Oct. 1991, pp. 358--364

Digital Library

[9]

Jimmy Liu Chien-Nan, Chang Chen-Yi, Jou Jing-Yang, Lai Ming-Chih, Juan Hsing-Ming, "A novel approach for functional coverage measurement in HDL Circuits and Systems", ISCAS2000: The 2000 IEEE International Symposium on Circuits and Systems, pp 217--220, 2000

[10]

E. Sanchez, M. Sonza Reorda and G. Squillero, "Test Program Generation From High-level Microprocessor Descriptions", Test and validation of hardware/software systems starting from system-level descriptions, Ed. M. Sonza Reorda, M. Violante, Z. Peng, Springer publisher, 179 p, ISBN: 1-85233-899-7, pp. 83--106, Dec. 2004

[11]

K. Jayaraman, V. M. Vedula and J. A. Abraham, "Native Mode Functional Self-test Generation for System-on-Chip", IEEE International Symposium on Quality Electronic Design (ISQED'02), pp. XX--XX, 2002

Digital Library

[12]

E. Sanchez, L. Veiras Bolzani, M. Sonza Reorda, "On Test Program Generation for Peripheral Components in a SoC Resorting to High-Level Metrics", {accepted for publication on} 8th IEEE Latin-American Test Workshop, LATW2007.

[13]

R. Chandramouli and S. Pateras, "Testing Systems on a Chip," IEEE Spectrum, Nov. 1996, pp. 1081--1093.

Digital Library

[14]

F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero, "Efficient Machine-Code Test-Program Induction", CEC2002: IEEE Congress on Evolutionary Computation, Honolulu, Hawaii (USA), pp. 1486--1491

Digital Library

[15]

F. Corno, E. Sanchez, G. Squillero, "Evolving Assembly Programs: How Games Help Microprocessor Validation", IEEE Transactions on Evolutionary Computation, Special Issue on Evolutionary Computation and Games, Dec. 2005, vol. 9, pp. 695--706

Digital Library

[16]

http://aspspider.org/alexsalo/

[17]

http://www.opencores.org

Cited By

Bolzani LSanchez ESchillaci MSquillero G(2007)Co-evolution of test programs and stimuli vectors for testing of embedded peripheral cores2007 IEEE Congress on Evolutionary Computation10.1109/CEC.2007.4424922(3474-3481)Online publication date: Sep-2007
https://doi.org/10.1109/CEC.2007.4424922

Index Terms

Coupling EA and high-level metrics for the automatic generation of test blocks for peripheral cores
1. Hardware
  1. Hardware test
  2. Robustness

Recommendations

An evolutionary methodology for test generation for peripheral cores via dynamic FSM extraction
Evo'08: Proceedings of the 2008 conference on Applications of evolutionary computing

Traditional test generation methodologies for peripheral cores are performed by a skilled test engineer, leading to long generation times. In this paper a test generation methodology based on an evolutionary tool which exploits high level metrics is ...
Automatic generation of test sets for SBST of microprocessor IP cores
SBCCI '05: Proceedings of the 18th annual symposium on Integrated circuits and system design

Higher integration densities, smaller feature lengths, and other technology advances, as well as architectural evolution, have made microprocessor cores exceptionally complex. Currently, Software-Based Self-Test (SBST) is becoming an attractive test ...
High-level test synthesis with hierarchical test generation for delay-fault testability

A high-level test synthesis (HLTS) method targeted for delay-fault testability is presented in this paper. The proposed method, when combined with hierarchical test-pattern generation for embedded modules, guarantees a 100% delay test coverage for ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

GECCO '07: Proceedings of the 9th annual conference on Genetic and evolutionary computation

July 2007

2313 pages

ISBN:9781595936974

DOI:10.1145/1276958

General Chair:
Hod Lipson
Cornell University, USA

Copyright © 2007 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 07 July 2007

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Conference

GECCO07

Sponsor:

GECCO07: Genetic and Evolutionary Computation Conference

July 7 - 11, 2007

London, England

Acceptance Rates

GECCO '07 Paper Acceptance Rate 266 of 577 submissions, 46%;

Overall Acceptance Rate 1,669 of 4,410 submissions, 38%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

1
Total Citations
View Citations
150
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 13 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

Bolzani LSanchez ESchillaci MSquillero G(2007)Co-evolution of test programs and stimuli vectors for testing of embedded peripheral cores2007 IEEE Congress on Evolutionary Computation10.1109/CEC.2007.4424922(3474-3481)Online publication date: Sep-2007
https://doi.org/10.1109/CEC.2007.4424922

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents