Article

Robust wiring networks for DfY considering timing constraints

Authors:

Philipp V. Panitz,

Markus Olbrich,

Erich Barke,

Jürgen KoehlAuthors Info & Claims

GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI

Pages 43 - 48

https://doi.org/10.1145/1228784.1228800

Published: 11 March 2007 Publication History

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Abstract

In nanometer technologies the importance of opens as yield detractors considerably increases. This requires to reconsider traditional tree based routing approaches for signal wiring. We propose a Greedy Minimum Routing Tree Augmentation (GMRTA) algorithm that shows significantly better results than previous approaches. The algorithm adds links to routing trees, thus increases its robustness against open defects. By exploiting that edges in multiple loops can be removed the augmentation efficiency is further improved. As a special feature, our algorithm keeps timing constraints which have not been considered by previous GMRTA algorithms.

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Cited By

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Yan J(2020)Single-Layer Delay-Driven GNR Nontree Routing Under Resource Constraint for Yield ImprovementIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.294198128:3(736-749)Online publication date: Mar-2020
https://doi.org/10.1109/TVLSI.2019.2941981
Yan J(2012)Resource-constrained link insertion for delay reductionIntegration10.1016/j.vlsi.2012.02.00745:4(349-356)Online publication date: Sep-2012
https://doi.org/10.1016/j.vlsi.2012.02.007
Yan JChen ZBahar RLombardi FAtienza DBrunvand E(2010)Resource-constrained timing-driven link insertion for critical delay reductionProceedings of the 20th symposium on Great lakes symposium on VLSI10.1145/1785481.1785510(119-122)Online publication date: 16-May-2010
https://dl.acm.org/doi/10.1145/1785481.1785510
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Index Terms

Robust wiring networks for DfY considering timing constraints
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing

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Published In

GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI

March 2007

626 pages

ISBN:9781595936059

DOI:10.1145/1228784

General Chairs:
Hai Zhou
Northwestern University
,
Enrico Macii
Politecnico di Torino
,
Program Chairs:
Zhiyuan Yan
Lehigh University
,
Yehia Massoud
Rice University

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 11 March 2007

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GLSVLSI07: Great Lakes Symposium on VLSI 2007

March 11 - 13, 2007

Stresa-Lago Maggiore, Italy

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Yan J(2020)Single-Layer Delay-Driven GNR Nontree Routing Under Resource Constraint for Yield ImprovementIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.294198128:3(736-749)Online publication date: Mar-2020
https://doi.org/10.1109/TVLSI.2019.2941981
Yan J(2012)Resource-constrained link insertion for delay reductionIntegration10.1016/j.vlsi.2012.02.00745:4(349-356)Online publication date: Sep-2012
https://doi.org/10.1016/j.vlsi.2012.02.007
Yan JChen ZBahar RLombardi FAtienza DBrunvand E(2010)Resource-constrained timing-driven link insertion for critical delay reductionProceedings of the 20th symposium on Great lakes symposium on VLSI10.1145/1785481.1785510(119-122)Online publication date: 16-May-2010
https://dl.acm.org/doi/10.1145/1785481.1785510
Chang FTsay RMak WRoychowdhury J(2009)How to consider shorts and guarantee yield rate improvement for redundant wire insertionProceedings of the 2009 International Conference on Computer-Aided Design10.1145/1687399.1687407(33-38)Online publication date: 2-Nov-2009
https://dl.acm.org/doi/10.1145/1687399.1687407
Yan JChen ZLombardi FBhanja SMassoud YBahar R(2009)Redundant wire insertion for yield improvementProceedings of the 19th ACM Great Lakes symposium on VLSI10.1145/1531542.1531635(409-412)Online publication date: 10-May-2009
https://dl.acm.org/doi/10.1145/1531542.1531635
Chen ZYan J(2009)Optimal transformation of non-tree topologies for timing analysis2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia)10.1109/PRIMEASIA.2009.5397446(69-72)Online publication date: Nov-2009
https://doi.org/10.1109/PRIMEASIA.2009.5397446
Panitz POlbrich MBarke EBuehler MKoehl JNarayanan VYan ZMacii EBhanja S(2008)Considering possible opens in non-tree topology wire delay calculationProceedings of the 18th ACM Great Lakes symposium on VLSI10.1145/1366110.1366118(17-22)Online publication date: 4-May-2008
https://dl.acm.org/doi/10.1145/1366110.1366118
Panitz POlbrich MBarke EBuehler MKoehl J(2008)Design of robust signal and clock networksPAMM10.1002/pamm.2007004687:1(1070205-1070206)Online publication date: 7-Sep-2008
https://doi.org/10.1002/pamm.200700468
Rizzo OMelzner HLevitan S(2007)Concurrent wire spreading, widening, and fillingProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278569(350-353)Online publication date: 4-Jun-2007
https://dl.acm.org/doi/10.1145/1278480.1278569

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Timing-Constrained Yield-Driven Wiring Reconstruction for Critical Area Minimization

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A yield-driven gridless router

Timing-Constrained Yield-Driven Wiring Reconstruction for Critical Area Minimization

Robust mixed-size placement under tight white-space constraints

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