Article

Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers

Authors:

Masanao Yamaoka,

Takayuki KawaharaAuthors Info & Claims

GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI

Pages 529 - 533

https://doi.org/10.1145/1228784.1228789

Published: 11 March 2007 Publication History

Abstract

Deep-sub-100-nm CMOS LSIs using a bulk CMOS device and a planar double-gate FD-SOI device are compared in terms of the low-voltage limitation of RAM cells, sense amplifiers, and logic gates. The limitation strongly depends on the ever-larger VT variation, especially in SRAM cells and logic gates, and is improved by the FD-SOI. Consequently, two possible LSIs are predicted to coexist in the deep-sub-100-nm generation: High-VDD bulk CMOS LSIs for low-cost low-standby-current applications, and low-VDD FD-SOI LSIs for low-power applications.

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Cited By

ITOH KYAMAOKA MOSHIMA T(2010)Adaptive Circuits for the 0.5-V Nanoscale CMOS EraIEICE Transactions on Electronics10.1587/transele.E93.C.216E93-C:3(216-233)Online publication date: 2010
https://doi.org/10.1587/transele.E93.C.216
Horiguchi MItoh KHoriguchi MItoh K(2010)Reduction Techniques for Margin Errors of Nanoscale MemoriesNanoscale Memory Repair10.1007/978-1-4419-7958-2_5(157-201)Online publication date: 26-Nov-2010
https://doi.org/10.1007/978-1-4419-7958-2_5
Itoh K(2009)Adaptive circuits for the 0.5-V nanoscale CMOS era2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers10.1109/ISSCC.2009.4977291(14-20)Online publication date: Feb-2009
https://doi.org/10.1109/ISSCC.2009.4977291
Show More Cited By

Index Terms

Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory

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Published In

cover image ACM Conferences

GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI

March 2007

626 pages

ISBN:9781595936059

DOI:10.1145/1228784

General Chairs:
Hai Zhou
Northwestern University
,
Enrico Macii
Politecnico di Torino
,
Program Chairs:
Zhiyuan Yan
Lehigh University
,
Yehia Massoud
Rice University

Copyright © 2007 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 11 March 2007

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GLSVLSI07: Great Lakes Symposium on VLSI 2007

March 11 - 13, 2007

Stresa-Lago Maggiore, Italy

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

ITOH KYAMAOKA MOSHIMA T(2010)Adaptive Circuits for the 0.5-V Nanoscale CMOS EraIEICE Transactions on Electronics10.1587/transele.E93.C.216E93-C:3(216-233)Online publication date: 2010
https://doi.org/10.1587/transele.E93.C.216
Horiguchi MItoh KHoriguchi MItoh K(2010)Reduction Techniques for Margin Errors of Nanoscale MemoriesNanoscale Memory Repair10.1007/978-1-4419-7958-2_5(157-201)Online publication date: 26-Nov-2010
https://doi.org/10.1007/978-1-4419-7958-2_5
Itoh K(2009)Adaptive circuits for the 0.5-V nanoscale CMOS era2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers10.1109/ISSCC.2009.4977291(14-20)Online publication date: Feb-2009
https://doi.org/10.1109/ISSCC.2009.4977291
Itoh KHoriguchi M(2009)Low-voltage scaling limitations for nano-scale CMOS LSIsSolid-State Electronics10.1016/j.sse.2008.09.02353:4(402-410)Online publication date: Apr-2009
https://doi.org/10.1016/j.sse.2008.09.023
Kiyoo Itoh Masashi Horiguchi Masanao Yamaoka (2007)Low-voltage limitations of memory-rich nano-scale CMOS LSIsESSDERC 2007 - 37th European Solid State Device Research Conference10.1109/ESSDERC.2007.4430883(68-75)Online publication date: Sep-2007
https://doi.org/10.1109/ESSDERC.2007.4430883
Kiyoo Itoh Masashi Horiguchi Masanao Yamaoka (2007)Low-voltage limitations of memory-rich nano-scale CMOS LSIsESSCIRC 2007 - 33rd European Solid-State Circuits Conference10.1109/ESSCIRC.2007.4430250(68-75)Online publication date: Sep-2007
https://doi.org/10.1109/ESSCIRC.2007.4430250

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