Article

A superblock-based flash translation layer for NAND flash memory

Authors:

Jeong-Uk Kang,

Heeseung Jo,

Jin-Soo Kim,

Joonwon LeeAuthors Info & Claims

EMSOFT '06: Proceedings of the 6th ACM & IEEE International conference on Embedded software

Pages 161 - 170

https://doi.org/10.1145/1176887.1176911

Published: 22 October 2006 Publication History

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Abstract

In NAND flash-based storage systems, an intermediate software layer called a flash translation layer (FTL)is usually employed to hide the erase-before-write characteristics of NAND flash memory. This paper proposes a novel superblockbased FTL scheme, which combines a set of adjacent logical blocks into a superblock. In the proposed FTL scheme, superblocks are mapped at coarse granularity,while pages inside the superblock are mapped freely at fine granularity to any location in several physical blocks. To reduce extra storage and flash memory operations, the fine-grain mapping information is stored in the spare area of NAND flash memory. This hybrid mapping technique has the flexibility provided by fine-grain address translation, while reducing the memory overhead to the level of coarse-grain address translation. Our experimental results show that the proposed FTL scheme decreases the garbage collection overhead up to 40% compared to previous FTL schemes.

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Papon TChen TZhang SAthanassoulis M(2024)CAVE: Concurrency-Aware Graph Processing on SSDsProceedings of the ACM on Management of Data10.1145/36549282:3(1-26)Online publication date: 30-May-2024
https://dl.acm.org/doi/10.1145/3654928
Wu JCai ZYang FLi JTrahay FYang ZWang CLiao J(2024)Polling Sanitization to Balance I/O Latency and Data Security of High-density SSDsACM Transactions on Storage10.1145/363982620:2(1-23)Online publication date: 19-Feb-2024
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Wang SLin ZWu SJiang HZhang JMao B(2024)LearnedFTL: A Learning-Based Page-Level FTL for Reducing Double Reads in Flash-Based SSDs2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA57654.2024.00054(616-629)Online publication date: 2-Mar-2024
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Index Terms

A superblock-based flash translation layer for NAND flash memory
1. Software and its engineering
  1. Software organization and properties
    1. Contextual software domains
      1. Operating systems
        Memory management
        Garbage collection

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Published In

EMSOFT '06: Proceedings of the 6th ACM & IEEE International conference on Embedded software

October 2006

346 pages

ISBN:1595935428

DOI:10.1145/1176887

General Chairs:
Sang Lyul Min
Seoul National University
,
Wang Yi
Uppsala University

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 22 October 2006

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ESWEEK06: Second Embedded Systems Week 2006

October 22 - 25, 2006

Seoul, Korea

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Overall Acceptance Rate 60 of 203 submissions, 30%

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Papon TChen TZhang SAthanassoulis M(2024)CAVE: Concurrency-Aware Graph Processing on SSDsProceedings of the ACM on Management of Data10.1145/36549282:3(1-26)Online publication date: 30-May-2024
https://dl.acm.org/doi/10.1145/3654928
Wu JCai ZYang FLi JTrahay FYang ZWang CLiao J(2024)Polling Sanitization to Balance I/O Latency and Data Security of High-density SSDsACM Transactions on Storage10.1145/363982620:2(1-23)Online publication date: 19-Feb-2024
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Wang SLin ZWu SJiang HZhang JMao B(2024)LearnedFTL: A Learning-Based Page-Level FTL for Reducing Double Reads in Flash-Based SSDs2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA57654.2024.00054(616-629)Online publication date: 2-Mar-2024
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A hybrid SSD with PRAM and NAND Flash memory

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