Article

Fault and energy-aware communication mapping with guaranteed latency for applications implemented on NoC

Authors:

Sorin Manolache,

Petru Eles,

Zebo PengAuthors Info & Claims

DAC '05: Proceedings of the 42nd annual Design Automation Conference

Pages 266 - 269

https://doi.org/10.1145/1065579.1065648

Published: 13 June 2005 Publication History

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Abstract

As feature sizes shrink, transient failures of on-chip network links become a critical problem. At the same time, many applications require guarantees on both message arrival probability and response time. We address the problem of transient link failures by means of temporally and spatially redundant transmission of messages, such that designerimposed message arrival probabilities are guaranteed. Response time minimisation is achieved by a heuristic that statically assigns multiple copies of each message to network links, intelligently combining temporal and spatial redundancy. Concerns regarding energy consumption are addressed in two ways. Firstly, we reduce the total amount of transmitted messages, and, secondly, we minimise the application response time such that the resulted time slack can be exploited for energy savings through voltage reduction. The advantages of the proposed approach are guaranteed message arrival probability and guaranteed worst case application response time.

References

[1]

A. Andrei, M. Schmitz, P. Eles, Z. Peng, and B. Al-Hashimi. Simultaneous communication and processor voltage scaling for dynamic and leakage energy reduction in time-constrained systems. In Proc. of ICCAD, 2004.

Digital Library

Google Scholar

[2]

L. Benini and G. De Micheli. Networks on chips: a new SoC paradigm. IEEE Computer, 35(1):70--78, 2002.

Digital Library

Google Scholar

[3]

D. Bertozzi, L. Benini, and G. De Micheli. Low power error resilient encoding for on-chip data buses. In Proc. of DATE, pages 102--109, 2002.

Digital Library

Google Scholar

[4]

W. Dally. Interconnect-limited VLSI architecture. In IEEE Conference on Interconnect Technologies, pages 15--17, 1999.

Crossref

Google Scholar

[5]

J. Dielissen, A. Radulescu, K. Goossens, and E. Rijpkema. Concepts and implementation of the Philips network-on-chip. In IP-Based SoC Design, 2003.

Google Scholar

[6]

T. Dumitras and R. Marculescu. On-chip stochastic communication. In Proc. of DATE, 2003.

Digital Library

Google Scholar

[7]

F. Glover. Tabu search-Part I. ORSA J. Comput., 1989.

Digital Library

Google Scholar

[8]

J. Hu and R. Marculescu. DyAD-Smart routing for Network-on-Chip. In Proc. of DAC, 2004.

Digital Library

Google Scholar

[9]

D. Liu et al. Power consumption estimation in CMOS VLSI chips. IEEE J. of Solid-State Circuits, (29):663--670, 1994.

Google Scholar

[10]

S. Manolache. Fault-tolerant communication on network-on-chip. Technical report, Linkoping Univ., 2004.

Google Scholar

[11]

J. C. Palencia Gutiérrez and M. González Harbour. Schedulability analysis for tasks with static and dynamic offsets. In Proceedings of the 19th IEEE Real Time Systems Symposium, pages 26--37, December 1998.

Digital Library

Google Scholar

[12]

M. Pirretti, G. M. Link, R. R. Brooks, N. Vijaykrishnan, M. Kandemir, and I. M. J. Fault tolerant algorithms for network-on-chip interconnect. In Proc. of the ISVLSI, 2004.

Crossref

Google Scholar

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Chen WWang XSun YHu QHuang LJiang YSingh AMak TYang M(2021)Evolution of Publications, Subjects, and Co-Authorships in Network-on-Chip Research From a Complex Network PerspectiveIEEE Access10.1109/ACCESS.2021.31231069(149399-149422)Online publication date: 2021
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Index Terms

Fault and energy-aware communication mapping with guaranteed latency for applications implemented on NoC
1. Hardware
  1. Hardware test
  2. Hardware validation

Recommendations

Fault-aware Communication Mapping for NoCs with Guaranteed Latency
As feature sizes shrink, transient failures of on-chip network links become a critical problem. At the same time, many applications require guarantees on both message arrival probability and response time. We address the problem of transient link failures ...
Fault-aware communication mapping for NoCs with guaranteed latency

As feature sizes shrink, transient failures of on-chip network links become a critical problem. At the same time, many applications require guarantees on both message arrival probability and response time. We address the problem of transient link ...
Software implemented hardware fault tolerance

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Information & Contributors

Information

Published In

DAC '05: Proceedings of the 42nd annual Design Automation Conference

June 2005

984 pages

ISBN:1595930582

DOI:10.1145/1065579

General Chair:
William H. Joyner
IBM Corp./SRC
,
Program Chairs:
Grant E. Martin
Tensilica, Inc.
,
Andrew B. Kahng
University of California at San Diego, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 June 2005

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DAC05: The 42nd Annual Design Automation Conference 2005

June 13 - 17, 2005

California, Anaheim, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Chen WWang XSun YHu QHuang LJiang YSingh AMak TYang M(2021)Evolution of Publications, Subjects, and Co-Authorships in Network-on-Chip Research From a Complex Network PerspectiveIEEE Access10.1109/ACCESS.2021.31231069(149399-149422)Online publication date: 2021
https://doi.org/10.1109/ACCESS.2021.3123106
Salimi MMajd ALoni MSeceleanu TSeceleanu CSirjani MDaneshtalab MTroubitsyna E(2019)Multi-objective Optimization of Real-Time Task Scheduling Problem for Distributed EnvironmentsProceedings of the 6th Conference on the Engineering of Computer Based Systems10.1145/3352700.3352713(1-9)Online publication date: 2-Sep-2019
https://dl.acm.org/doi/10.1145/3352700.3352713
Nejatollahi HDutt NRay SRegazzoni FBanerjee ICammarota R(2019)Post-Quantum Lattice-Based Cryptography ImplementationsACM Computing Surveys10.1145/329254851:6(1-41)Online publication date: 28-Jan-2019
https://dl.acm.org/doi/10.1145/3292548
Majd ASahebi GDaneshtalab MTroubitsyna E(2017)Optimizing scheduling for heterogeneous computing systems using combinatorial meta-heuristic solution2017 IEEE SmartWorld, Ubiquitous Intelligence & Computing, Advanced & Trusted Computed, Scalable Computing & Communications, Cloud & Big Data Computing, Internet of People and Smart City Innovation (SmartWorld/SCALCOM/UIC/ATC/CBDCom/IOP/SCI)10.1109/UIC-ATC.2017.8397655(1-8)Online publication date: Aug-2017
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Kiani VReshadi M(2017)Mapping multiple applications onto 3D NoC-based MPSoCs supporting wireless linksThe Journal of Supercomputing10.1007/s11227-016-1908-373:5(2187-2213)Online publication date: 1-May-2017
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Haque MEom YHe YElnikety SBianchini RMcKinley K(2015)Few-to-ManyACM SIGPLAN Notices10.1145/2775054.269438450:4(161-175)Online publication date: 14-Mar-2015
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Fault-aware Communication Mapping for NoCs with Guaranteed Latency

Fault-aware communication mapping for NoCs with guaranteed latency

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