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Logic verification system for very large computers using LSI's

Authors:

Yasuhiro Ohno,

Masayuki Miyoshi,

Katsuya SatoAuthors Info & Claims

DAC '79: Proceedings of the 16th Design Automation Conference

Pages 367 - 374

Published: 25 June 1979 Publication History

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Abstract

To aid design verification of very large computers using many LSI's, software tools including a logic simulator with capability of 750,000 gates have been developed.

References

[1]

1) E. G. Ulrich, "Exclusive simulation of activity in digital networks," Comm of the ACM, pp. 102-110, February 1969.

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[2]

2) S. A. Szygenda and E. W. Thompson, "Digital logic simulation in a time-based table-driven environment, Part 1, Design verification," Computer, pp. 24-36, March 1975.

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[3]

3) S. G. Chappell, P. R. Menon, J. F. Pellegrin, and A. M. Schowe, "Functional simulation in the LAMP system," J. of Design Automation & Fault Tolerant Computing, pp. 203-215, May 1977.

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Kazama YKinoshita YNagafuji MMurayama HShaklee DNewton A(1988)Algorithm for vectorizing logic simulation and evaluation of “VELVET” performanceProceedings of the 25th ACM/IEEE Design Automation Conference10.5555/285730.285768(231-236)Online publication date: 1-Jun-1988
https://dl.acm.org/doi/10.5555/285730.285768
Miyoshi MOoshima YSugiyama AOnizuka NAmano NThomas D(1986)An extensive logic simulation method of very large scale computer designProceedings of the 23rd ACM/IEEE Design Automation Conference10.5555/318013.318070(360-365)Online publication date: 2-Jul-1986
https://dl.acm.org/doi/10.5555/318013.318070
Miyoshi MKazama YTada ONagura YAmano NOfek HO'Neill L(1985)Speed up techniques of logic simulationProceedings of the 22nd ACM/IEEE Design Automation Conference10.5555/317825.318003(812-815)Online publication date: 1-Jun-1985
https://dl.acm.org/doi/10.5555/317825.318003
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Logic verification system for very large computers using LSI's

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DAC '79: Proceedings of the 16th Design Automation Conference

June 1979

578 pages

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IEEE Press

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Published: 25 June 1979

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Kazama YKinoshita YNagafuji MMurayama HShaklee DNewton A(1988)Algorithm for vectorizing logic simulation and evaluation of “VELVET” performanceProceedings of the 25th ACM/IEEE Design Automation Conference10.5555/285730.285768(231-236)Online publication date: 1-Jun-1988
https://dl.acm.org/doi/10.5555/285730.285768
Miyoshi MOoshima YSugiyama AOnizuka NAmano NThomas D(1986)An extensive logic simulation method of very large scale computer designProceedings of the 23rd ACM/IEEE Design Automation Conference10.5555/318013.318070(360-365)Online publication date: 2-Jul-1986
https://dl.acm.org/doi/10.5555/318013.318070
Miyoshi MKazama YTada ONagura YAmano NOfek HO'Neill L(1985)Speed up techniques of logic simulationProceedings of the 22nd ACM/IEEE Design Automation Conference10.5555/317825.318003(812-815)Online publication date: 1-Jun-1985
https://dl.acm.org/doi/10.5555/317825.318003
Ulrich EHebert DCrabbe JRadke COfek H(1982)Speed and accuracy in digital network simulation based on structural modelingProceedings of the 19th Design Automation Conference10.5555/800263.809263(587-593)Online publication date: 1-Jan-1982
https://dl.acm.org/doi/10.5555/800263.809263
Kamikawai RYamada MChiba TFurumaya KTsuchiya Y(1981)A critical path delay check systemProceedings of the 18th Design Automation Conference10.5555/800073.802289(118-123)Online publication date: 29-Jun-1981
https://dl.acm.org/doi/10.5555/800073.802289
Yamada A(1981)Design automation status in JapanProceedings of the 18th Design Automation Conference10.5555/800073.802278(43-50)Online publication date: 29-Jun-1981
https://dl.acm.org/doi/10.5555/800073.802278
Sasaki TYamada AKato SNakazawa TTomita KNomizu NHassler ESmith RPistilli PAbel LCrabbe JBening LShaklee DRadke C(1980)MIXSProceedings of the 17th Design Automation Conference10.1145/800139.804596(626-633)Online publication date: 23-Jun-1980
https://dl.acm.org/doi/10.1145/800139.804596

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A Layout System for the Random Logic Portion of an MOS LSI Chip

Lsi circuit simulation on vector computers (spice2, classie)

Nanosecond threshold logic gates for 16 X 16 bit, 80 ns LSI multiplier

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A Layout System for the Random Logic Portion of an MOS LSI Chip

Lsi circuit simulation on vector computers (spice2, classie)

Nanosecond threshold logic gates for 16 X 16 bit, 80 ns LSI multiplier

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