Non-Volatile Memory Technologies

Recent trends of aggressive technology scaling have greatly exacerbated the occurrences and impact of faults in computing systems. This has made `reliability' a first-order design constraint. To address the challenges of reliability, several techniques have been proposed. This paper provides a survey of architectural techniques for improving resilience of computing systems. We especially focus on techniques proposed for microarchitectural components, such as processor registers, functional units, cache and main memory etc. In addition, we discuss techniques proposed for non-volatile memory (NVM), GPUs and 3D-stacked processors. To underscore the similarities and differences of the techniques, we  classify them based on their key characteristics. We also review the metrics proposed to quantify vulnerability of processor structures. We believe that this survey will help researchers, system-architects and processor designers in gaining insights into the techniques for improving reliability of computing systems.

Non-volatile memories (NVMs) offer superior density and energy characteristics compared to the conventional memories; however, NVMs suffer from severe reliability issues that can easily eclipse their energy efficiency advantages. In this paper, we survey architectural techniques for improving the soft-error reliability of NVMs, specifically PCM (phase change memory) and STT-RAM (spin transfer torque RAM). We focus on soft-errors, such as resistance drift and write disturbance, in PCM and read disturbance and write failures in STT-RAM. By classifying the research works based on key parameters, we highlight their similarities and distinctions. We hope that this survey will underline the crucial importance of addressing NVM reliability for ensuring their system integration and will be useful for researchers, computer architects and processor designers.

RAM adalah kependekan dari Random Access Memory. RAM merupakan sebuah perangkat keras atau hardware yang digunakan untuk menyimpan data sementara atau memori. Selain menyimpan data, fungsi RAM adalah untuk menyimpan berbagai jenis instruksi program pada sebuah komputer. RAM merupakan memory utama yang merupakan jenis volatile memory, artinya data yang ada di RAM hanya akan bertahan saat ada arus listrik. Berbeda dengan cara kerja hardisk. Hardisk adalah non volatile memory. Disebut Random Access Memory karena dapat diakses secara acak. Artinya, RAM bisa diakses tanpa tergantung pada tata letak data. Selain itu, RAM juga merupakan sistem penyimpanan yang sifatnya sementara, tidak seperti hardisk yang merupakan penyimpanan permanen.

Learning from a few examples (one/few-shot learning) on the fly is a key challenge for on-device machine intelligence. We present the first chip-level demonstration of one-shot learning with Stanford Associative memory for Programmable, Integrated Edge iNtelligence via lifelong learning and Search (SAPIENS), a resistive random access memory (RRAM)-based non-volatile associative memory (AM) chip that serves as the backend for memory-augmented neural networks (MANNs). The 64-kb fully integrated RRAM-CMOS AM chip performs long-term feature embedding and retrieval, demonstrated on a 32-way one-shot learning task on the Omniglot dataset. Using only one example per class for 32 unseen classes during onchip learning, SAPIENS achieves 79% measured inference accuracy on Omniglot, comparable to edge software model accuracy using five-level quantization (82%). It achieves an energy efficiency of 118 GOPS/W at 200 MHz for in-memory L1 distance computation and prediction. Multi-bank measurements on the same chip show that increasing the capacity from three banks (24 kb) to eight banks (64 kb) improves the chip accuracy from 73.5% to 79%, while minimizing the accuracy excursion due to bank-to-bank variability.

In this paper, we evaluate the potentiality of hafnium aluminium oxide (HfAlO) high-k materials for control dielectric application in non-volatile memories. We analyze the electrical properties (conduction and parasitic trapping) of HfAlO single layers and SiO2/HfAlO/SiO2 triple layer stacks as a function of the HfAlO thickness and Hf:Al ratio. A particular attention is given to the electrical behaviour of the samples at high temperature, up to 250°C. Experimental results obtained on silicon nanocrystal memories demonstrate the high advantage of HfAlO based control dielectrics on the memory performances for Fowler–Nordheim operation. Then an analytical model is presented, to simulate the program erase characteristics in the transient regime and at saturation, depending on the high-k control dielectric properties. A very good agreement is obtained between the experimental data and the simulation results.

Source-code: https://code.ornl.gov/3d_cache_modeling_tool/destiny. PDF of extended technical report http://goo.gl/qzyWFE]

The continuous drive for performance has pushed the researchers to explore novel memory technologies (e.g. nonvolatile memory) and novel fabrication approaches (e.g. 3D stacking) in the design of caches. However, a comprehensive tool which models both conventional and emerging memory technologies for both 2D and 3D designs has been lacking. We present DESTINY, an architecture-level tool for modeling 3D (and 2D) cache designs using SRAM, embedded DRAM(eDRAM), spin transfer torque RAM (STT-RAM), resistive RAM (ReRAM) and phase change RAM (PCM). DESTINY facilitates design-space exploration across several dimensions, such as optimizing for a target (e.g. latency or area) for a given memory technology, choosing the suitable memory technology or fabrication method (i.e. 2D v/s 3D) for a desired optimization target etc. DESTINY has been validated against industrial cache prototypes. We believe that DESTINY will drive architecture and system-level studies and will be useful for researchers, designers and marketing professionals.

Advancements in electronics research triggered a vision of a more connected world, touching new unprecedented fields to improve the quality of our lives. This vision has been fueled by electronic giants showcasing flexible displays for the first time in consumer electronics symposiums. Since then, the scientific and research communities partook on exploring possibilities for making flexible electronics. Decades of research have revealed many routes to flexible electronics, lots of opportunities and challenges. In this work, we focus on our contributions towards realizing a complimentary approach to flexible inorganic high performance electronic memories on silicon. This approach provides a straight forward method for capitalizing on the existing well-established semiconductor infrastructure, standard processes and procedures, and collective knowledge. Ultimately, we focus on understanding the reliability and functionality anomalies in flexible electronics and flexible solid state memory built using the flexible silicon platform. The results of the presented studies show that: (i) flexible devices fabricated using etch-protect-release approach (with trenches included in the active area) exhibit ~19% lower safe operating voltage compared to their bulk counterparts, (ii) they can withstand prolonged bending duration (static stress) but are prone to failure under dynamic stress as in repeated bending and re-flattening, (iii) flexible 3D FinFETs exhibit ~10% variation in key properties when exposed to out-of-plane bending stress and out-of-plane stress does not resemble the well-studied in-plane stress used in strain engineering, (iv) resistive memories can be achieved on flexible silicon and their basic resistive property is preserved but other memory functionalities (retention, endurance, speed, memory window) requires further investigations, (v) flexible silicon based PZT ferroelectric capacitors exhibit record polarization, capacitance, and endurance (1 billion write-erase cycles) values for flexible FeRAMs, uncompromised retention ability under varying dynamic stress, and a minimum bending radius of 5 mm, and (vi) the combined effect of 225 °C, 260 MPa tensile stress, 55% humidity under ambient conditions (21% oxygen), led to 48% reduction in switching coercive fields, 45% reduction in remnant polarization, an expected increase of 22% in relative permittivity and normalized capacitance, and reduced memory window (20% difference between switching and non-switching currents at 225 °C).

To improve the security of mobile management is to identify and analyze the needs of wireless mobility that revolve around the protection modules data lost or stolen devices through remote functions To achieve this, it was first necessary to apply data prevention strategies, ensures the encryption of compliance by blocking devices unbridled or unencrypted for it must be given an intelligence vision, through securing the different mobile data components of its technical architecture. To isolate mobile data analysis queries and operational queries. As analysis requests are often very cumbersome, the main objective was to preserve the performance of the mobile operating systems. Then this database dedicated to queries and analysis gradually transferred and organized.

This paper is an introduction to flash memory forensics with a special focus on completeness of evidence acquired from mobile phones. Moving through academic papers and industrial documents will be introduced the particular nature of non-volatile memories present in nowadays mobile phones; how they really work and which challenges they pose to forensic investigators. Then will be presented an advanced test in which some brand new flash memories have been used to hide data in man-made bad blocks: the aim is to verify if forensic software tools are able to acquire data from such blocks, and to evaluate the possibility to hide data at analysts’ eyes.

The work presented in this paper had two main objectives. The first objective was to develop a very stable nanosecond infrared pulsed fiber laser oscillator platform offering a straightforward and accurate control over the pulse characteristics in the time domain. The second objective was to deliver what we call "high quality photons", which means delivering pulses with high energy and excellent beam quality and narrow spectral linewidth, all at the same time and with very good stability. Oscillators with such attributes find applications in material processing fields, for example in memory repair, photovoltaic cell processing or micro-milling, to name just a few. In order to achieve the first objective, an embedded digital platform using high-speed electronics was developed. Using this platform and a computer, pulse shapes have been programmed straightforwardly in the non-volatile memory of the instrument, with an amplitude resolution of 10 bits and a time resolution of 2.5 ns. Optical pulses having tailored temporal profiles, with rise times around 1 ns and pulse energy stability levels better than +/- 3% at 3σ, have been generated at high repetition rates (> 100 kHz) at a wavelength of 1064 nm. Achieving the second objective required amplifying the low power master oscillator signal (10-100 mW) to output power levels in the range of 1 to 50 W. A multi-clad, polarization maintaining, Yb-doped large mode area fiber was specially designed to allow for the amplification of high peak power optical pulses, while keeping control over the nonlinear effects and preserving an excellent beam quality. Optical pulses with tailored shapes and pulse energy levels in excess of 140 μJ have been produced for pulse durations in the range of 10 to 80 ns, with 86% of the power emitted in a 0.5-nm bandwidth. The linearly polarized beam M2 parameter was smaller than 1.1, with both the astigmatism and the asymmetry below 15%. The pulse energy stability was better than +/- 3% at 3σ. We conclude with a discussion about some of the applications of the developed platform.

Alumina is a key material for developing innovative Charge-Trapping Non-Volatile Memory (CT-NVM) devices. Al2O3 is used to implement the top dielectric in TANOS devices, and it has been proposed as trapping layer and to engineer the tunnel dielectric. Despite the large use of this material, the quantitative investigation of defect features still lacks. In this scenario, the purpose of this work is to investigate the physics of electron/hole trapping/detrapping mechanisms in Al2O3. Combining I-V and C-V measurements with a physical model we derive the energy levels of electron/hole traps and the location of electron/hole charge. The influence of electron/hole alumina traps on TANOS operations and reliability is investigated.

Numerous candidates attempting to replace Si-based flash memory have failed for a variety of reasons over the years. Oxide-based resistance memory and the related memristor have succeeded in surpassing the specifications for a number of device requirements. However, a material or device structure that satisfies high-density, switching-speed, endurance, retention and most importantly power-consumption criteria has yet to be announced. In this work we demonstrate a TaOx-based asymmetric passive switching device with which we were able to localize resistance switching and satisfy all aforementioned requirements. In particular, the reduction of switching current drastically reduces power consumption and results in extreme cycling endurances of over 1012. Along with the 10 ns switching times, this allows for possible applications to the working-memory space as well. Furthermore, by combining two such devices each with an intrinsic Schottky barrier we eliminate any need for a discrete transistor or diode in solving issues of stray leakage current paths in high-density crossbar arrays.

A previous version, published as a technical report, is available here https://www.academia.edu/4249420/Energy_Saving_Techniques_for_Phase_Change_Memory_PCM_

The demands of larger memory capacity in high-performance computing systems have motivated the researchers to explore alternatives of DRAM (dynamic random access memory). Since PCM (phase change memory) provides high-density, good scalability and non-volatile data storage, it has received significant amount of attention in recent years. A crucial bottleneck in wide-spread adoption of PCM, however, is that its write latency and energy are very high. Recently, several architecture and system-level techniques have been proposed to address this issue. In this paper, we survey several techniques for managing power consumption of PCM. We also classify these techniques based on their characteristics to highlight their similarities and differences. The aim of this paper  is to provide insights to researchers into working of PCM power-management techniques and also motivate them to  propose even better techniques for designing future `green' PCM-based main memory  systems.

HfO2-based resistive RAM (RRAM) is an emerging nonvolatile memory technology that has recently been shown capable of storing multiple bits-per-cell. The energy/delay costs of an RRAM write operation are dependent on the number of pulses required for RRAM programming. The pulse count is often large when existing programming approaches are used for multiple bits-per-cell RRAM, especially when resistance ranges are allocated to account for retention. We present a new technique, Range-Dependent Adaptive Resistance (RADAR) Tuning, for fast and energy-efficient programming of multiple bits-per-cell RRAM arrays, using a combination of coarse-and fine-grained RRAM resistance tuning. Experimental data are collected on 16k cells from two 1Megacell (1M physical cells) 1T1R HfO2-based RRAM arrays fabricated in a 130-nm CMOS process. RADAR reduces the programming pulse count by 2.4X (for both uncycled cells and cells that have undergone 8k cycles) on average over existing programming techniques tested on the same RRAM arrays, with the same bit error rate targets.