Microelectronics

Presented here is a patent in the Bulgarian register of inventions (Reg. № 27611/1974), written in Bulgarian. The patent relates to novel types of leads for various semiconductor devices: integrated circuits, photodiodes, modular packaged discrete devices, etc. The new leads configuration is proposed in order to avoid some of the disadvantages of the existing ones. Illustrated are several examples of assemblies demonstrating the advantages and the versatility of packaging methods applying this novel leads configuration.

The invention described features two claims. The description is supported by five drawings.

Focuses on the importance of ceramic tapes as a substrate material for hybrid microelectronic circuits. Fabrication of thermal reactor; Importance in monitoring temperature; Utilization of layered manufacturing and rapid prototyping processes.

Less than 116 ps overall clock skew has been achieved across the 15.02 mm/spl times/15.03 mm die by balanced clock path routing and differential clock signal distribution in the global clock tree of 300 MHz 128-bit 2-way superscalar microprocessor. The shared clock wire configuration and clock buffer layout patterns over the whole die enhance the clock skew insensitivity to process

SEMATECH has sponsored a “Test Method Evaluation” study to understand the trade-offs among the most common test methodologies used in the industry. This paper presents the results of the failure analysis portion of that project. The testing, reliability stressing, characterization, fault diagnosis and physical analysis results are presented for 25 devices including “IDDq-only” failures and “delay test-only” failures

In this paper, a methodology for the development of fault-tolerant adders based on the radix 2 signed digit (SD) representation is presented. The use of a number representation characterized by a carry propagation confined to neighbor digits implies interesting advantages in terms of error detection, fault localization, and repair. Errors caused by faults belonging to a considered stuck-at fault set can be detected by a parity-based technique. In fact, a carry-free adder preserving the parity of the augends can be implemented allowing fault detection by using a parity checker. Regarding fault localization, the "carry-free" property of the adder ensures the confinement of the error due to a permanent fault to only few digits. The detection of the faulty digit has been obtained by using a recomputation with shifted operands method. Finally, after the fault localization, graceful degradation of the system intended as the reduction of the performances versus a correct output computation can be obtained by using two different procedures. The first one allows obtaining the correct output by recomputing the result performing two different shift operations and using the intersection of the obtained results to recover the correct output, while the second one is based on a reduced dynamic range approach, which allows us to obtain the result in only one step, but with fewer output digits.

The thick film NixZn(1−x)Fe2O4 on alumina substrate was prepared by screen printing of the ferrite powder synthesized by chemical co-precipitation method using nitrate precursors. These NixZn(1−x)Fe2O4 thick films of varying x were characterized by X-ray diffraction, FTIR spectroscopy and SEM (scanning electron microscopy). The permittivity and permeability were measured by overlay technique. Voltage standing wave ratio method was also used to measure the dielectric constant. The permittivity was found to increase with Ni content varying between 13 and 18. The permeability was ∼3.01. The overlay technique provides an easy method for measurement of permittivity and permeability of ferrite thick film.

Thin silicon dioxide (SiO2) films nitrided by rapid thermal processing (RTP) in ammonia and nitrous oxide are compared. Their electrical characteristics (oxide and interface trapped charge densities, resistance to high-field stress, breakdown charge) are correlated with the concentration of nitrogen at the Si/SiO2 interface. An optimum in several parameters is found for very light nitridations (0·5-1 at.% N). In this case, a significant improvement in the reliability of non-volatile memories (EEPROMs) is anticipated.

Power dissipation is expected to increase exponentially to 150-250 W per chip over the next decade. To manage this large heat output, it is necessary to minimize the thermal resistance between the chip and a heat dissipation unit that the device is attached to. It is therefore important to further improve the thermal performance of thermal interface materials (TIMs), which can be achieved through 1) improvement of the bulk thermal conductivity of TIMs; and/or 2) reduction of interfacial thermal resistances between the TIM and the device and/or TIM and the heat dissipation unit. The latter improvement may be obtained by enhanced physical properties of TIMs (e.g., viscosity or wetting ability) and/or surface modification of the heat dissipation unit or the inactive side of the device. Researchers have tried to take advantage of the high 1D thermal conductivities of graphite fibers, and more recently of carbon nanotubes (CNT), to reduce the thermal resistance between the chip and the h...

Inkjet printing is the emerging technology for the deposition of a variety of particles. The reliable printing of nano-silver inks shows the possibilities of digital fabrication of microelectronic circuits and raises the question for further use with other particles. To compete with common thick-film screen printing as a production method it is consequential and necessary to investigate the inkjet printing of all passive electronic thick-film components. Inductors are frequently required in electronic circuits, yet they represent a main challenge for thick-film printing. With the development of new materials, which are suitable for low-temperature cofired ceramic processes, the integration of passive components promises new applications. In a first step, different ferrite particle compositions are dispersed to stabilized inks that can be used with a commercial inkjet print head. The stability of the ink is fundamental for reliable drop formation. In addition, the viscosity must fit ...

In this paper the author presents an analog VLSI circuit to implement the synapse operation in artificial neural network systems. This circuit is a two-quadrant (or four-quadrant) analog multiplier. The output of the synapse circuit is in current and it is proportional to the multiplication of two input voltages: the weight voltage and the pattern information input voltage (or the output voltage of the neuron). The main feature of the multiplier is the high value of the weight voltage range, which varies between the ground voltage and the supply voltage [0:Vdd]

Peça fundamental dos transmissores e receptores de radiofrequência, os misturadores possuem diversas topologias e estudos relacionados. O foco deste trabalho e desenvolver um misturador passivo utilizando como base trabalhos do estado da arte buscando aprimora-los para a tecnologia 65 nm disponível para a concepção deste trabalho. O objetivo e fazer com que o misturador possa filtrar sinais indesejados ao mesmo tempo que faz a conversão em frequência e que funcione em faixas de frequência onde ser ˆ a implementada a quinta geração de telefonia móvel (5G). A validação se dá comparando parâmetros de desempenho obtidos com os do estado da arte. Por fim, pretende-se desenvolver um layout na tecnologia selecionada para futuro uso com outros componentes de radiofrequência na mesma tecnologia abrindo caminho para o desenvolvimento de um transmissor ou receptor completo.

The presentation concerns a practical approach for dealing with difficulties associated to real time testing in a natural environment of microelectronic devices. This activity has several redeeming characteristics that make it very interesting for reliability engineers that are concerned with the Single Event Effects (SEEs) affecting the functioning of their devices in a natural working environment. The paramount advantage that the circuit behavior observed during the experiment will be identical to the effects that may appear during the useful lifetime of the product. Thus, the test results will closely match real- life scenario from both quantitative (event rate) and qualitative (types of events) perspectives. However, some difficulties are still present and may strongly impact the interest of this testing method. The first difficulty consists in obtaining a significant number of events in order to be able to compute statistical data with an adequate order of accuracy. This requirement has repercussions on the hardware test setAcircnot up and test protocol but also on the mathematical methods that will be used for result analysis. An appropriate test set-up for real-time testing should consist in a high number of same-type DUTs (Devices Under Test). This way, the event rate of a single device will be accelerated by the number of devices under test. This will have an obvious impact on the preparation of the experiment. The hardware board, tester, power supplies, and other instruments will have to be designed to support a large number of devices. To further accelerate the apparition frequency of the errors, the devices should operate in a natural working environment with a higher particle flux. Since the neutron flux increases with the altitude following a well known equation, we should place the test set-up (DUTs, tester, power supply, support instrumentation) in a high-altitude test facility. This facility could be either mobile (atmospheric balloon, dirigibles, a- irplanes, satellites, etc) or fixed (ground-level). In this presentation we only present our tests in mountain research stations such as Jungfraujoch, Swiss and Plateau de Bure, France, since these facilities benefits from all amenities (stable power main, internet access, lodging, accurate neutron flux monitoring) while still offering a good acceleration (15-20 times more neutrons compared to sea-level testing). In any case, the practical duration of real-time tests is quite long (several months). The second difficulty is related to the origin of the SEEs. Since internal radioactive impurities will produce alpha particles that may also cause SEEs, we will need to discriminate the contribution of external and internal perturbations. Accelerated radiation testing doesn't present this problems, since the test times are very short (few hours), making the relative contributions of alpha particles very low. However, since real-time testing is performed during several months, the alpha particles cannot be ignored. Thus, we should be able to measure/estimate the contribution of the alpha particles to the Soft Error Rate of the circuit. Two approaches are possible. The first one consists in measuring the error count of the devices placed in a shielded environment (such as a cave or an underground tunnel) where the contribution of neutrons can be minimized, or estimating the alpha SER using the alpha emissivity of the package (measured through alpha-counting) and sensitivity results from dedicated alpha testing on exposed silicon dies. The third difficulty consists in correctly analyzing the test results. The low event rate requires adequate mathematical methods. Other possible external perturbations or set-up instability may cause additional errors that could mix with SEE-induced errors. Lastly, since the experiment will run during a long period of time, the test set-up will have to be controlled and monitored remotely. Additionally, the neutron atmospheric flux should b