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Automatic test program generation for pipelined processors

Published: 09 March 2003 Publication History

Abstract

The continuous advances in microelectronics design are creating a significant challenge to design validation in general, but tackling piplined microprocessors is remarkably more demanding. This paper presents a methodology to automatically induce a test program for a microprocessor maximizing a given verification metric. The approach exploits a new evolutionary algorithm, close to Genetic Programming, able to cultivate effective assembly-language programs. The proposed methodology was used to verify the DLX/pII, an open-source processor with a 5-stage pipeline. Code-coverage was adopted in the paper, since it can be considered the required starting point for any simulation-based functional verification processes. Experimental results clearly show the effectiveness of the approach.

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cover image ACM Conferences
SAC '03: Proceedings of the 2003 ACM symposium on Applied computing
March 2003
1268 pages
ISBN:1581136242
DOI:10.1145/952532
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 09 March 2003

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