Article

Compiler optimization of scalar value communication between speculative threads

Authors:

Christopher B. Colohan,

J. Gregory Steffan,

Todd C. MowryAuthors Info & Claims

ASPLOS X: Proceedings of the 10th international conference on Architectural support for programming languages and operating systems

Pages 171 - 183

https://doi.org/10.1145/605397.605416

Published: 01 October 2002 Publication History

Abstract

While there have been many recent proposals for hardware that supports Thread-Level Speculation (TLS), there has been relatively little work on compiler optimizations to fully exploit this potential for parallelizing programs optimistically. In this paper, we focus on one important limitation of program performance under TLS, which is stalls due to forwarding scalar values between threads that would otherwise cause frequent data dependences. We present and evaluate dataflow algorithms for three increasingly-aggressive instruction scheduling techniques that reduce the critical forwarding path introduced by the synchronization associated with this data forwarding. In addition, we contrast our compiler techniques with related hardware-only approaches. With our most aggressive compiler and hardware techniques, we improve performance under TLS by 6.2-28.5% for 6 of 14 applications, and by at least 2.7% for half of the other applications.

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Compiler optimization of scalar value communication between speculative threads

While there have been many recent proposals for hardware that supports Thread-Level Speculation (TLS), there has been relatively little work on compiler optimizations to fully exploit this potential for parallelizing programs optimistically. In this ...
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Compiler optimization of scalar value communication between speculative threads
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While there have been many recent proposals for hardware that supports Thread-Level Speculation (TLS), there has been relatively little work on compiler optimizations to fully exploit this potential for parallelizing programs optimistically. In this ...

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cover image ACM Conferences

ASPLOS X: Proceedings of the 10th international conference on Architectural support for programming languages and operating systems

October 2002

318 pages

ISBN:1581135742

DOI:10.1145/605397

Conference Chair:
Kourosh Gharachorloo
Compaq Western Research Lab
,
Program Chair:
David A. Wood

ACM SIGARCH Computer Architecture News Volume 30, Issue 5
Special Issue: Proceedings of the 10th annual conference on Architectural Support for Programming Languages and Operating Systems
December 2002
296 pages
ISSN:0163-5964
DOI:10.1145/635506
Issue’s Table of Contents
ACM SIGOPS Operating Systems Review Volume 36, Issue 5
December 2002
296 pages
ISSN:0163-5980
DOI:10.1145/635508
Issue’s Table of Contents
ACM SIGPLAN Notices Volume 37, Issue 10
October 2002
296 pages
ISSN:0362-1340
EISSN:1558-1160
DOI:10.1145/605432
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Published: 01 October 2002

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Cited By

Ying VJeffrey MSanchez D(2020)T4: Compiling Sequential Code for Effective Speculative Parallelization in Hardware2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA)10.1109/ISCA45697.2020.00024(159-172)Online publication date: May-2020
https://doi.org/10.1109/ISCA45697.2020.00024
Doi KShioya RAndo H(2018)Performance Improvement Techniques in Tightly Coupled Multicore Architectures for Single-Thread ApplicationsJournal of Information Processing10.2197/ipsjjip.26.44526(445-460)Online publication date: 2018
https://doi.org/10.2197/ipsjjip.26.445
Lattuada MPilato CFerrandi F(2016)Performance Estimation of Task Graphs Based on Path ProfilingInternational Journal of Parallel Programming10.1007/s10766-015-0372-744:4(735-771)Online publication date: 1-Aug-2016
https://dl.acm.org/doi/10.1007/s10766-015-0372-7
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Campanoni SBrownell KKanev SJones TWei GBrooks D(2014)HELIX-RCACM SIGARCH Computer Architecture News10.1145/2678373.266570542:3(217-228)Online publication date: 14-Jun-2014
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