A Soft-Error Mitigation Approach Using Pulse Quenching Enhancement at Detailed Placement for Combinational Circuits
Article No.: 65, Pages 1 - 22
Abstract
As technology continuously shrinks, radiation-induced soft errors have become a great threat to the circuit reliability. Among all the causes, the Single-Event Transient (SET) effect is the dominating one for the radiation-induced soft errors. SET-induced soft errors can be mitigated by multiple methods. In terms of area and power overhead, blocking SET propagation is considered to be the most efficient way for soft error reduction. It is found that the SET pulse width can be shrunk by a pulse quenching effect, which can be utilized to mitigate soft errors without introducing any area and power overhead. In this article, we present an effective detailed placer to exploit the pulse quenching effect for soft error reduction in combinational circuits. In our method, the quenching effect enhancement is globally optimized while the cell displacement is minimized. The experimental results demonstrate that our method reduces the soft error vulnerability of the circuits by 29.53% versus 18.38% of the state-of-the-art solution. Meanwhile, our method has a minimal effect on the displacement and half-perimeter wire length (HPWL) compared with the previous solutions, which means a minimum timing influence to the original design.
References
[1]
J. R. Ahlbin, M. J. Gadlage, and D. R. Ball. 2010. The effect of layout topology on single-event transient pulse quenching in a 65 nm bulk CMOS process. IEEE Transactions on Nuclear Science 57, 6 (2010), 3380–3385.
[2]
Jonathan R. Ahlbin, Lloyd W. Massengill, Bharat L. Bhuva, Balaji Narasimham, Matthew J. Gadlage, and Paul H. Eaton. 2009. Single-event transient pulse quenching in advanced CMOS logic circuits. IEEE Transactions on Nuclear Science 56, 6 (2009), 3050–3056.
[3]
L. Amaru, P. E. Gaillardon, and G. De Micheli. 2015. The EPFL combinational benchmark suite. Proceedings of the 24th International Workshop on Logic and Synthesis (IWLS) (2015).
[4]
L. Artola and G. Hubert. 2016. Pulse quenching induced by multi-collection effects in 45 nm silicon-on-insulator technology. Semiconductor Science and Technology 31, 12 (2016), 124002.
[5]
Nicholas M. Atkinson, Arthur F. Witulski, W. Timothy Holman, Jonathan R. Ahlbin, Bharat L. Bhuva, and Lloyd W. Massengill. 2011. Layout technique for single-event transient mitigation via pulse quenching. IEEE Transactions on Nuclear Science 58, 3 (2011), 885–890.
[6]
Zhong Zhi Bai. 2010. Modulus-based matrix splitting iteration methods for linear complementarity problems. Numerical Linear Algebra with Applications 17, 6 (2010), 917–933.
[7]
Liang Bin and Du Yankang. 2013. Two sides of pulse quenching effect on the single-event transient pulse width at circuit-level. Proceedings of International Conference on ASIC (2013), 1–4.
[8]
Michel Briet and Arnaud Verdant. 2009. Logic cell with two isolated redundant outputs, and corresponding integrated circuit. (2009). US Patent 7,550,992.
[9]
D. Bryan. 1985. The ISCAS’85 benchmark circuits and netlist format. North-Carolina State University (1985).
[10]
T. Calin, M. Nicolaidis, and R. Velazco. 1996. Upset hardened memory design for submicron CMOS technology. IEEE Transactions on Nuclear Science 43, 6 (1996), 2874–2878.
[11]
C. L. Chen and M. Y. Hsiao. 1984. Error-correcting codes for semiconductor memory applications: A state-of-the-art review. IBM Journal of Research and Development 28, 2 (1984), 124–134.
[12]
Jianli Chen, Ziran Zhu, Wenxing Zhu, and Yao-Wen Chang. 2017. Toward optimal legalization for mixed-cell-height circuit designs. In Proceedings of the 54th Annual Design Automation Conference 2017. Article 52, 6 pages.
[13]
Shuming Chen, D. U. Yankang, and Biwei Liu. 2012. A mixed-mode simulation method and tool for computing SER in combinational logic. Journal of National University of Defense Technology 34, 4 (2012), 153–157.
[14]
Yankang Du, Shuming Chen, and Biwei Liu. 2013. A constrained layout placement approach to enhance pulse quenching effect in large combinational circuits. IEEE Transactions on Device and Materials Reliability 14, 1 (2013), 268–274.
[15]
Yankang Du, Shuming Chen, and Biwei Liu. 2013. Impact of pulse quenching effect on soft error vulnerabilities in combinational circuits based on standard cells. Microelectronics Journal 44, 2 (2013), 65–71.
[16]
H. Dussault, J. W. Howard, R. C. Block, M. R. Pinto, W. J. Stapor, and R. Knudson. 1994. High energy heavy-ion-induced single event transients in epitaxial structures. IEEE Transactions on Nuclear Science 41, 6 (1994), 2018–2025.
[17]
Mojtaba Ebrahimi, Hossein Asadi, Rajendra Bishnoi, and Mehdi B. Tahoori. 2016. Layout-based modeling and mitigation of multiple event transients. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 35, 3 (2016), 367–379.
[18]
Luis Entrena, Almudena Lindoso, Enrique San Millan, Samuel Pagliarini, Felipe Almeida, and Fernanda Kastensmidt. 2012. Constrained placement methodology for reducing SER under single-event-induced charge sharing effects. IEEE Transactions on Nuclear Science 59, 4 (2012), 811–817.
[19]
V. Ferlet-Cavrois, P. Paillet, D. McMorrow, et al.2007. New insights into single event transient propagation in chains of inverters-evidence for propagation-induced pulse broadening. IEEE Transactions on Nuclear Science 54, 6 (2007), 2338–2346.
[20]
Wu Gao. 2018. Design Theories and Methods of Radiation-hardened CMOS Integrated Circuits. Tsinghua University Press.
[21]
Bradley T. Kiddie and William Robinson. 2014. Alternative standard cell placement strategies for single-event multiple-transient mitigation. IEEE Computer Society Annual Symposium on VLSI (2014), 589–594.
[22]
Bradley T. Kiddie and William H. Robinson. 2016. Relative logic cell placement for mitigation of charge sharing-induced transients. Semiconductor Science and Technology 31, 10 (2016), 104002.
[23]
Bradley T. Kiddie, William H. Robinson, and Daniel B. Limbrick. 2015. Single-event multiple-transient characterization and mitigation via alternative standard cell placement methods. ACM Transactions on Design Automation of Electronic Systems (TODAES) 20, 4 (2015), 60.
[24]
Chang Liu, Xu He, Bin Liang, and Yang Guo. 2018. Detailed placement for pulse quenching enhancement in anti-radiation combinational circuit design. Integration, VLSI 62 (2018), 182–189.
[25]
Nihaar N. Mahatme, Indranil Chatterjee, Akash Patki, Daniel B. Limbrick, Bharat L. Bhuva, Ronald D. Schrimpf, and William Robinson. 2013. An efficient technique to select logic nodes for single event transient pulse-width reduction. Microelectronics Reliability 53, 1 (2013), 114–117.
[26]
James Munkres. 1957. Algorithms for the assignment and transportation problems. J. Soc. Indust. Appl. Math. 5, 1 (1957), 32–38.
[27]
O. Musseau. 1996. Single-event effects in SOI technologies and devices. IEEE Transactions on Nuclear Science 43, 2 (1996), 603–613.
[28]
Balaji Narasimham, Jody W. Gambles, Robert L. Shuler, Bharat L. Bhuva, and Lloyd W. Massengill. 2008. Quantifying the effect of guard rings and guard drains in mitigating charge collection and charge spread. IEEE Transactions on Nuclear Science 55, 6 (2008), 3456–3460.
[29]
B. Narasimham, R. L. Shuler, J. D. Black, B. L. Bhuva, R. D. Schrimpf, A. F. Witulski, W. T. Holman, and L. W. Massengill. 2007. Quantifying the effectiveness of guard bands in reducing the collected charge leading to soft errors. In 2007 45th Annual IEEE International Reliability Physics Symposium Proceedings. IEEE, 676–677.
[30]
M. Nicolaidis. 1999. Time redundancy based soft-error tolerance to rescue nanometer technologies. Proc. VLSI Test Symposium (1999).
[31]
Brian D. Olson, Oluwole A. Amusan, Sandeepan Dasgupta, Lloyd W. Massengill, and Dennis R. Ball. 2007. Analysis of parasitic PNP bipolar transistor mitigation using well contacts in 130 nm and 90 nm CMOS technology. IEEE Transactions on Nuclear Science 54, 4 (2007), 894–897.
[32]
Samuel Pagliarini, Fernanda Kastensmidt, Luis Entrena, Almudena Lindoso, and Enrique San Millan. 2011. Analyzing the impact of single-event-induced charge sharing in complex circuits. IEEE Transactions on Nuclear Science 58, 6 (2011), 2768–2775.
[33]
Samuel N. Pagliarini and Dhiraj Pradhan. 2014. A placement strategy for reducing the effects of multiple faults in digital circuits. In 2014 IEEE 20th International On-Line Testing Symposium (IOLTS). IEEE, 69–74.
[34]
Selahattin Sayil and Nareshkumar B. Patel. 2010. Soft error and soft delay mitigation using dynamic threshold technique. IEEE Transactions on Nuclear Science 57, 6 (2010), 3553–3559.
[35]
Sandeep Shambhulingaiah, Lawrence T. Clark, Thomas J. Mozdzen, Nathan D. Hindman, Srivatsan Chella, and Keith E. Holbert. 2011. Temporal sequential logic hardening by design with a low power delay element. In 2011 12th European Conference on Radiation and Its Effects on Components and Systems. IEEE, 144–149.
[36]
Wu Zhenyu, Chen Shuming, Chen Jianjun, and Huang Pengcheng. 2018. Impacts of proton radiation on heavy-ion-induced single-event transients in 65-nm CMOS technology. IEEE Transactions on Nuclear Science (2018).
[37]
Quming Zhou and Kartic Mohanram. 2004. Transistor sizing for radiation hardening. In 2004 Proceedings of IEEE International Reliability Physics Symposium. IEEE, 310–315.
Index Terms
- A Soft-Error Mitigation Approach Using Pulse Quenching Enhancement at Detailed Placement for Combinational Circuits
Recommendations
Detailed placement for pulse quenching enhancement in anti-radiation combinational circuit design
AbstractPulse width of single event transient can be shrunk by pulse quenching effect in combinational circuits. And it is found that the pulse quenching effect is closely related to the layout of the circuits. In this paper, we propose a ...
A Robust Mixed-Size Legalization and Detailed Placement Algorithm
Placement is one of the most important steps in the RTL-to-GDSII synthesis process as it directly defines the interconnects. The rapid increase in IC design complexity and the widespread use of intellectual-property blocks have made the so-called mixed-...
TSV-aware analytical placement for 3D IC designs
DAC '11: Proceedings of the 48th Design Automation ConferenceThrough-silicon vias (TSVs) are required for transmitting signals among different dies for the three-dimensional integrated circuit (3D IC) technology. The significant silicon areas occupied by TSVs bring critical challenges for 3D IC placement. Unlike ...
Comments
Information & Contributors
Information
Published In
July 2023
432 pages
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].
Publisher
Association for Computing Machinery
New York, NY, United States
Journal Family
Publication History
Published: 18 July 2023
Online AM: 05 May 2023
Accepted: 20 April 2023
Revised: 08 February 2023
Received: 17 October 2022
Published in TODAES Volume 28, Issue 4
Check for updates
Author Tags
Qualifiers
- Research-article
Funding Sources
- National Natural Science Foundation of China
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 188Total Downloads
- Downloads (Last 12 months)60
- Downloads (Last 6 weeks)8
Reflects downloads up to 30 Jan 2025
Other Metrics
Citations
View Options
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in