research-article

Hardware Optimizations of Fruit-80 Stream Cipher: Smaller than Grain

Authors:

Gangqiang Yang,

Hailiang Xiong,

Zhiguo WanAuthors Info & Claims

ACM Transactions on Reconfigurable Technology and Systems, Volume 16, Issue 2

Article No.: 22, Pages 1 - 32

https://doi.org/10.1145/3569455

Published: 11 March 2023 Publication History

Abstract

Fruit-80, which emerged as an ultra-lightweight stream cipher with 80-bit secret key, is oriented toward resource-constrained devices in the Internet of Things. In this article, we propose area and speed optimization architectures of Fruit-80 on FPGAs. Our implementations include both serial and parallel structure and optimize area, power, speed, and throughput, respectively. The area optimization architecture aims to achieve the most suitable ratio of look-up-tables and flip-flops to fully utilize the reconfigurable unit. It also reuses NFSR and LFSR feedback functions to save resources for high throughput. The speed optimization architecture adopts a hybrid approach for parallelization and reduces the latency of long data paths by pre-generating primary feedback and inserting flip-flops. Besides, we recommend using the round key function to optimize serial or parallel implementations for Fruit-80 and using indexing and shifting methods for different throughput. In conclusion, our results show that the area optimization architecture occupies up to 35 slices on Xilinx Spartan-3 FPGA and 18 slices on Xilinx 7 series FPGA, smaller than that of Grain and other common stream ciphers. The optimal throughput/area ratio of the speed optimization architecture is 7.74 Mbps/slice, better than that of Grain v1, which is 5.98 Mbps/slice. The serial implementation of Fruit-80 with round key function occupies only 75 slices on Spartan-3 FPGA. To the best of our knowledge, the result sets a new record of the minimum area in lightweight cipher implementation on FPGA.

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Index Terms

Hardware Optimizations of Fruit-80 Stream Cipher: Smaller than Grain
1. Hardware
  1. Integrated circuits
    1. Reconfigurable logic and FPGAs
2. Security and privacy
  1. Cryptography
    1. Symmetric cryptography and hash functions
      1. Block and stream ciphers
  2. Security in hardware
    1. Hardware security implementation

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cover image ACM Transactions on Reconfigurable Technology and Systems

ACM Transactions on Reconfigurable Technology and Systems Volume 16, Issue 2

June 2023

451 pages

ISSN:1936-7406

EISSN:1936-7414

DOI:10.1145/3587031

Editor:
Deming Chen
University of Illinois, Urbana-Champaign, USA

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Publication History

Published: 11 March 2023

Online AM: 25 October 2022

Accepted: 08 October 2022

Revised: 31 August 2022

Received: 02 June 2022

Published in TRETS Volume 16, Issue 2

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Major Basic Research Program of the Shandong Provincial Natural Science Foundation
Research Program of the Shandong Provincial Natural Science Foundation
National Natural Science Foundation of China
Open Fund of State Key Laboratory of Integrated Services Networks
Qingdao Science and Technology Program
Zhejiang Provincial Department of Science and Technology 2021 annual key R&D plan

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Shi ZChen CYang GZhou HXiong HWan Z(2024)Customized FPGA Implementation of Authenticated Lightweight Cipher Fountain for IoT SystemsACM Transactions on Embedded Computing Systems10.1145/364303924:2(1-26)Online publication date: 26-Jan-2024
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Schmid MArul TKavun ERegazzoni FKara O(2024)Robust and Energy-efficient Hardware Architectures for DIZY Stream Cipher2024 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)10.1109/APCCAS62602.2024.10808577(461-465)Online publication date: 7-Nov-2024
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