research-article

TARUC: A Topology-Aware Resource Usability and Contention Benchmark

Authors:

Gavin Baker,

Chris LupoAuthors Info & Claims

ICPE '17: Proceedings of the 8th ACM/SPEC on International Conference on Performance Engineering

Pages 305 - 316

https://doi.org/10.1145/3030207.3030230

Published: 17 April 2017 Publication History

Get Access

Abstract

Computer architects have increased hardware parallelism and power efficiency by integrating massively parallel hardware accelerators (coprocessors) into compute systems. Many modern HPC clusters now consist of multi-CPU nodes along with additional hardware accelerators in the form of graphics processing units (GPUs). Each CPU and GPU is integrated with system memory via communication links (QPI and PCIe) and multi-channel memory controllers. The increasing density of these heterogeneous computing systems has resulted in complex performance phenomena including non-uniform memory access (NUMA) and resource contention that make application performance hard to predict and tune. This paper presents the Topology Aware Resource Usability and Contention (TARUC) benchmark. TARUC is a modular, open-source, and highly configurable benchmark useful for profiling dense heterogeneous systems to provide insight for developers who wish to tune application codes for specific systems. Analysis of TARUC performance profiles from a multi-CPU, multi-GPU system is also presented.

References

[1]

G. Baker. An emperical study of contention and NUMA effects on heterogeneous computing systems. Master's thesis, California Polytechnic State University, June 2016.

Google Scholar

[2]

L. Bergstrom. Measuring NUMA Effects With the STREAM Benchmark. arXiv preprint arXiv:1103.3225, 2011.

Google Scholar

[3]

F. Gaud, B. Lepers, J. Decouchant, J. Funston, A. Fedorova, and V. Quéma. Large Pages May be Harmful on NUMA Systems. In 2014 USENIX Annual Technical Conference (USENIX ATC 14), pages 231--242, 2014.

Google Scholar

[4]

Intel. White paper: An Introduction to the ÂŹQuickPath Interconnect. Technical report, Intel Corporation, January 2009.

Google Scholar

[5]

P. Jacob, A. Zia, O. Erdogan, P. M. Belemjian, J.-W. Kim, M. Chu, R. P. Kraft, J. F. McDonald, and K. Bernstein. Mitigating Memory Wall Effects in High-Clock-Rate and Multicore CMOS 3-D Processor Memory Stacks. Proceedings of the IEEE, 97(1):108--122, 2009.

Crossref

Google Scholar

[6]

J. Lawley. White paper: Understanding Performance of PCI Express Systems. Technical report, XILINX, October 2014.

Google Scholar

[7]

S. A. McKee. Reflections on the Memory Wall. In Proceedings of the 1st conference on Computing frontiers, page 162. ACM, 2004.

Digital Library

Google Scholar

[8]

K. Spafford, J. S. Meredith, and J. S. Vetter. Quantifying NUMA and Contention Effects in Multi-GPU Systems. In Proceedings of the Fourth Workshop on General Purpose Processing on Graphics Processing Units, page 11. ACM, 2011.

Digital Library

Google Scholar

[9]

C. Su, D. Li, D. S. Nikolopoulos, M. Grove, K. Cameron, and B. R. De Supinski. Critical Path-Based Thread Placement for NUMA Systems. ACM SIGMETRICS Performance Evaluation Review, 40(2):106--112, 2012.

Digital Library

Google Scholar

[10]

The Top500 List of Supercomputers. http://www.top500.org. Accessed: 2016-4-14.

Google Scholar

Cited By

View all

Trochatos TEtim ASzefer J(2024)Covert-channels in FPGA-enabled SmartSSDsACM Transactions on Reconfigurable Technology and Systems10.1145/363531217:2(1-23)Online publication date: 30-Apr-2024
https://dl.acm.org/doi/10.1145/3635312
Tian SGiechaskiel IXiong WSzefer J(2023)Fingerprinting and Mapping Cloud FPGA InfrastructuresSecurity of FPGA-Accelerated Cloud Computing Environments10.1007/978-3-031-45395-3_9(239-272)Online publication date: 18-Sep-2023
https://doi.org/10.1007/978-3-031-45395-3_9
Giechaskiel ITian SSzefer J(2023)Contention-Based Threats Between Single-Tenant Cloud FPGA InstancesSecurity of FPGA-Accelerated Cloud Computing Environments10.1007/978-3-031-45395-3_6(137-172)Online publication date: 18-Sep-2023
https://doi.org/10.1007/978-3-031-45395-3_6
Show More Cited By

Index Terms

TARUC: A Topology-Aware Resource Usability and Contention Benchmark

Recommendations

Memory Access Characterization of Scientific Applications on GPU and Its Implication on Low Power Optimization
ICCIS '11: Proceedings of the 2011 International Conference on Computational and Information Sciences

Following current IC design technology trend, modern GPUs integrate more and more processing cores, and the speed gap between processor and memory system becomes even larger. As the number of cores continually increases, the available bandwidth per core ...
Performance evaluation of intel's quad core processors for embedded applications

Recently, multiprocessing is implemented using either chip multiprocessing (CMP) or Simultaneous multithreading (SMT). Multi-core processors, represent CMP processors, are widely used in desktop and server applications and are now appearing in real-time ...
Scaling up matrix computations on shared-memory manycore systems with 1000 CPU cores
ICS '14: Proceedings of the 28th ACM international conference on Supercomputing

While the growing number of cores per chip allows researchers to solve larger scientific and engineering problems, the parallel efficiency of the deployed parallel software starts to decrease. This unscalability problem happens to both vendor-provided ...

Comments

Information & Contributors

Information

Published In

ICPE '17: Proceedings of the 8th ACM/SPEC on International Conference on Performance Engineering

April 2017

450 pages

ISBN:9781450344043

DOI:10.1145/3030207

General Chairs:
Walter Binder
Università della Svizzera Italiana, Switzerland
,
Vittorio Cortellessa
Università dell'Aquila, Italy
,
Program Chairs:
Anne Koziolek
Karlsruhe Institute of Technology, Germany
,
Evgenia Smirni
College of William & Mary, USA
,
Meikel Poess
Oracle Corporation, USA

Publication rights licensed to ACM. ACM acknowledges that this contribution was authored or co-authored by an employee, contractor or affiliate of the United States government. As such, the Government retains a nonexclusive, royalty-free right to publish or reproduce this article, or to allow others to do so, for Government purposes only.

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 17 April 2017

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Conference

ICPE '17

Sponsor:

ICPE '17: ACM/SPEC International Conference on Performance Engineering

April 22 - 26, 2017

L'Aquila, Italy

Acceptance Rates

ICPE '17 Paper Acceptance Rate 27 of 83 submissions, 33%;

Overall Acceptance Rate 252 of 851 submissions, 30%

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

5
Total Citations
View Citations
84
Total Downloads

Downloads (Last 12 months)1
Downloads (Last 6 weeks)0

Reflects downloads up to 15 Sep 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Trochatos TEtim ASzefer J(2024)Covert-channels in FPGA-enabled SmartSSDsACM Transactions on Reconfigurable Technology and Systems10.1145/363531217:2(1-23)Online publication date: 30-Apr-2024
https://dl.acm.org/doi/10.1145/3635312
Tian SGiechaskiel IXiong WSzefer J(2023)Fingerprinting and Mapping Cloud FPGA InfrastructuresSecurity of FPGA-Accelerated Cloud Computing Environments10.1007/978-3-031-45395-3_9(239-272)Online publication date: 18-Sep-2023
https://doi.org/10.1007/978-3-031-45395-3_9
Giechaskiel ITian SSzefer J(2023)Contention-Based Threats Between Single-Tenant Cloud FPGA InstancesSecurity of FPGA-Accelerated Cloud Computing Environments10.1007/978-3-031-45395-3_6(137-172)Online publication date: 18-Sep-2023
https://doi.org/10.1007/978-3-031-45395-3_6
Giechaskiel ITian SSzefer J(2021)Cross-VM Information Leaks in FPGA-Accelerated Cloud Environments2021 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)10.1109/HOST49136.2021.9702277(91-101)Online publication date: 12-Dec-2021
https://doi.org/10.1109/HOST49136.2021.9702277
Tian SGiechaskiel IXiong WSzefer J(2021)Cloud FPGA Cartography using PCIe Contention2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM51124.2021.00035(224-232)Online publication date: May-2021
https://doi.org/10.1109/FCCM51124.2021.00035

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Memory Access Characterization of Scientific Applications on GPU and Its Implication on Low Power Optimization

Performance evaluation of intel's quad core processors for embedded applications

Scaling up matrix computations on shared-memory manycore systems with 1000 CPU cores