research-article

A cross-layer approach for resiliency and energy efficiency in Near Threshold Computing

Authors:

M. S. Golanbari,

A. Gebregiorgis,

M. B. TahooriAuthors Info & Claims

2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

Pages 1 - 8

https://doi.org/10.1145/2966986.2980081

Published: 07 November 2016 Publication History

Abstract

Energy constrained systems become the cornerstone of emerging energy harvested or battery-limited applications in Internet of Thing (IoT) platforms. A promising approach is to operate at near threshold voltage ranges, which can significantly reduce energy per operation. However, due to increased sensitivity to variations and reduced noise margin at low voltages, resiliency becomes a major challenge. In this paper we provide a cross layer approach, from compiler all the way to circuit design, to maximize the energy efficiency as well as the resiliency of functional units. The key idea is to identify the instructions which become timing critical at low voltages and address them by a combination of circuit redesign, multi-cycle execution and code replacement. This allows us to significantly reduce timing failures and at the same time limit leakage energy, which becomes considerable at low voltages. This approach enables resilient and energy efficient operation in a wide voltage range to trade off energy and performance.

References

[1]

J. Gubbi et al., Internet of Things (IoT): A vision, architectural elements, and future directions. Future Generation Computer Systems, 29 (7): 1645–1660, 2013.

[2]

R. Dreslinski et al., Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits. Proc. IEEE, 98 (2): 253–266, 2010.

[3]

H. Kaul et al., Near-threshold voltage (NTV) design: opportunities and challenges. In DAC, pp. 1153–1158. 2012.

[4]

M. Seok et al., CAS-FEST 2010: Mitigating variability in near-threshold computing. IEEE J. Emerg. Sel. Topics Circuits Sys., 1 (1): 42–49, 2011.

[5]

B. H. Calhoun, A. Wang and A. Chandrakasan. Modeling and sizing for minimum energy operation in subthreshold circuits. IEEE J. Solid-State Circuits, 40 (9): 1778–1786, 2005.

[6]

R. Gonzalez, B. M. Gordon and M. A. Horowitz. Supply and threshold voltage scaling for low power CMOS. IEEE J. Solid-State Circuits, 32 (8): 1210–1216, 1997.

[7]

Y. K. Ramadass and A. P. Chandrakasan. Minimum energy tracking loop with embedded DC-DC converter enabling ultra-low-voltage operation down to 250 mV in 65 nm CMOS. IEEE J. Solid-state circuits, 43 (1): 256–265, 2008.

[8]

L. Koskinen et al., Implementing Minimum-Energy-Point Systems With Adaptive Logic. IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 24 (4): 1247–1256, 2016.

Digital Library

[9]

N. Mehta and K. A. Makinwa. Minimum energy point tracking for sub-threshold digital CMOS circuits using an in-situ energy sensor. In ISCAS, pp. 570–573. 2013.

[10]

M. R. Kakoee et al., Automatic synthesis of near-threshold circuits with fine-grained performance tunability. In ISLPED, pp. 401–406. 2010.

[11]

U. R. Karpuzcu et al., EnergySmart: toward energy-efficient manycores for near-threshold computing. In HPCA, pp. 542–553. 2013.

[12]

S. Seo et al., Process variation in near-threshold wide SIMD architectures. In DAC, pp. 980–987. 2012.

[13]

M. Wieckowski et al., Timing yield enhancement through soft edge flip-flop based design. In CICC, pp. 543–546. 2008.

[14]

V. Joshi, D. Blaauw and D. Sylvester. Soft-edge flip-flops for improved timing yield: design and optimization. In ICCAD, pp. 667–673. 2007.

[15]

G. Gammie et al., A 45nm 3.5 g baseband-and-multimedia application processor using adaptive body-bias and ultra-low-power techniques. In ISSCC, pp. 258–611. 2008.

[16]

M. S. Golanbari et al., Variation-aware near threshold circuit synthesis. In DATE, pp. 1237–1242. 2016.

[17]

E. Krimer et al., Synctium: a near-threshold stream processor for energy-constrained parallel applications. IEEE ComputerArchitecture Letters, 9 (1): 21–24, 2010.

Digital Library

[18]

K. Bowman et al., Circuit techniques for dynamic variation tolerance. In DAC, pp. 4–7. 2009.

[19]

D. Ernst et al., Razor: circuit-level correction of timing errors for low-power operation. IEEE Micro, 24 (6): 10–20, 2004.

Digital Library

[20]

B. Greskamp and J. Torrellas. Paceline: Improving single-thread performance in nanoscale CMPs through core over-clocking. In PACT, pp. 213–224. 2007.

[21]

S. G. Ramasubramanian et al., Relax-and-retime: A methodology for energy-efficient recovery based design. In DAC, pp. 1–6. 2013.

[22]

Y. Liu et al., On logic synthesis for timing speculation. In ICCAD, pp. 591–596. 2012.

[23]

F. Oboril et al., Negative bias temperature instability-aware instruction scheduling: A cross-layer approach. J. Low Power Electronics, 9 (4): 389–402, 2013.

[24]

F. Oboril et al., Reducing NBTI-induced processor wearout by exploiting the timing slack of instructions. In CODES+ISSS, pp. 443–452. ACM, 2012.

[25]

K. Kuhn et al., Process Technology Variation. IEEE Trans. Electron Devices, 58 (8): 2197–2208, Aug 2011.

[26]

S. Jain, et al. A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS. In ISSCC, pp. 66–68. 2012.

[27]

N. J. Wang et al., Characterizing the Effects of Transient Faults on a High-Performance Processor Pipeline. In DSN, pp. 61–71. 2004.

[28]

N. Binkert et al., The Gem5 Simulator. SIGARCH Comput. Archit. News, 39 (2): 1–7, 2011.

Digital Library

[29]

G. Hinton et al., The Microarchitecture of the Pentium 4 Processor. Intel Technology Journal, 1: 2001, 2001.

Cited By

Tonetto RNazar GBeck A(2025)A variation-aware methodology for improved processor designs for the edge computing domainDesign Automation for Embedded Systems10.1007/s10617-024-09291-129:1Online publication date: 1-Mar-2025
https://dl.acm.org/doi/10.1007/s10617-024-09291-1
Zhang ZGuo ZLin YWang RHuang RBolchini CO'Connor IVerbauwhede IWille R(2022)EventTimerProceedings of the 2022 Conference & Exhibition on Design, Automation & Test in Europe10.5555/3539845.3540065(945-950)Online publication date: 14-Mar-2022
https://dl.acm.org/doi/10.5555/3539845.3540065
Zhang ZGuo ZLin YWang RHuang R(2022)EventTimer: Fast and Accurate Event-Based Dynamic Timing Analysis2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE54114.2022.9774642(945-950)Online publication date: 14-Mar-2022
https://doi.org/10.23919/DATE54114.2022.9774642
Show More Cited By

Index Terms

A cross-layer approach for resiliency and energy efficiency in Near Threshold Computing

Index terms have been assigned to the content through auto-classification.

Recommendations

Yield-driven near-threshold SRAM design
ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

Voltage scaling is desirable in SRAM to reduce energy consumption. However, commercial SRAM is prone to functional failures when V_dd is scaled. Several SRAM designs scale V_dd to 200--300mV to minimize energy per access, but these designs do not consider ...
Temperature-Aware Dynamic Voltage Scaling to Improve Energy Efficiency of Near-Threshold Computing
Power and energy reduction is of uttermost importance for applications with stringent power/energy budget such as ultralow power and energy-harvested systems. Aggressive voltage scaling and in particular near-threshold computing is a promising approach to ...
Improving Performance under Process and Voltage Variations in Near-Threshold Computing Using 3D ICs

Near-threshold computing (NTC) circuits have been shown to offer significant energy efficiency and power benefits but with a huge performance penalty. This performance loss exacerbates if process and voltage variations are considered. In this article, ...

Comments

Information & Contributors

Information

Published In

cover image Guide Proceedings

2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

Nov 2016

946 pages

Copyright © 2016.

Publisher

IEEE Press

Publication History

Published: 07 November 2016

Permissions

Request permissions for this article.

Request Permissions

Qualifiers

Research-article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

10
Total Citations
View Citations
90
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 15 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

Tonetto RNazar GBeck A(2025)A variation-aware methodology for improved processor designs for the edge computing domainDesign Automation for Embedded Systems10.1007/s10617-024-09291-129:1Online publication date: 1-Mar-2025
https://dl.acm.org/doi/10.1007/s10617-024-09291-1
Zhang ZGuo ZLin YWang RHuang RBolchini CO'Connor IVerbauwhede IWille R(2022)EventTimerProceedings of the 2022 Conference & Exhibition on Design, Automation & Test in Europe10.5555/3539845.3540065(945-950)Online publication date: 14-Mar-2022
https://dl.acm.org/doi/10.5555/3539845.3540065
Zhang ZGuo ZLin YWang RHuang R(2022)EventTimer: Fast and Accurate Event-Based Dynamic Timing Analysis2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE54114.2022.9774642(945-950)Online publication date: 14-Mar-2022
https://doi.org/10.23919/DATE54114.2022.9774642
Tahoori MGolanbari M(2020)Cross-Layer Reliability, Energy Efficiency, and Performance Optimization of Near-Threshold Data PathsJournal of Low Power Electronics and Applications10.3390/jlpea1004004210:4(42)Online publication date: 3-Dec-2020
https://doi.org/10.3390/jlpea10040042
Gebregiorgis ABishnoi RTahoori M(2019)A Comprehensive Reliability Analysis Framework for NTC Caches: A System to Device ApproachIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.281869138:3(439-452)Online publication date: Mar-2019
https://doi.org/10.1109/TCAD.2018.2818691
Golanbari MGebregiorgis AMoradi EKiamehr STahoori MShin Y(2018)Balancing resiliency and energy efficiency of functional units in ultra-low power systemsProceedings of the 23rd Asia and South Pacific Design Automation Conference10.5555/3201607.3201754(637-644)Online publication date: 22-Jan-2018
https://dl.acm.org/doi/10.5555/3201607.3201754
Gebregiorgis ATahoori M(2018)Fine-Grained Energy-Constrained Microprocessor Pipeline DesignIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.276754326:3(457-469)Online publication date: 1-Mar-2018
https://dl.acm.org/doi/10.1109/TVLSI.2017.2767543
Bal ASaha SRoy SChakraborty K(2018)Dynamic Choke Sensing for Timing Error Resilience in NTC SystemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.275296326:1(1-10)Online publication date: Jan-2018
https://doi.org/10.1109/TVLSI.2017.2752963
Golanbari MGebregiorgis AMoradi EKiamehr STahoori M(2018)Balancing resiliency and energy efficiency of functional units in ultra-low power systems2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2018.8297394(637-644)Online publication date: Jan-2018
https://doi.org/10.1109/ASPDAC.2018.8297394
Golanbari MTahoori M(2017)Design flows for resilient energy-efficient systems2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)10.1109/IOLTS.2017.8046243(233-236)Online publication date: Jul-2017
https://doi.org/10.1109/IOLTS.2017.8046243

View Options

View options

Media

Figures

Other

Tables

View Table of Contents