2016 Proceeding
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Energy Efficient And Low Latency Interconnection Network For Multicast Invalidates In Shared Memory Systems
Optical network-on-chip (NoC) are being investigated to reduce the latency and power consumption of networks for multicore processors. Our previous work has shown that switched optical networks can achieve lower latency for a given power consumption and ...
Hierarchical Clustering for On-Chip Networks
Hierarchy and communication locality are a must for many-core systems. As systems scale to dozens or hundreds of cores, we simply cannot afford the power consumption and latency of random communication that spans the entire chip. Existing hierarchical ...
Evolutionary vs. Revolutionary Interconnect Technologies for Future Low-Power Multi-Core Systems
Networks-on-chip (NoCs) are today at the core of multi- and many-core systems, acting as the system-level integration framework. In order to support scaling to future device generations, NoCs will struggle to deliver the required communication ...
Designing an Efficient MPLS-Based Switch for FAT Tree Network-on-Chip Systems
This paper describes a proposal for FAT tree based Network-on-Chip system based on MPLS forwarding mechanism. The FAT tree includes processing nodes and communication switches. IP node (processing nodes) has a message generator unit which randomly ...
Consideration of the Flit Size for Deflection Routing based Network-on-Chips
Bufferless deflection routing enables energy and hardware efficient Network-on-Chips (NoCs). However, due to the lack of buffers, packet switching can not be deployed for such NoCs. Therefore, it is crucial to determine an appropriate flit size and link ...
Bringing OptoBoards to HPC-scale environments: An OptoHPC simulation engine
The increased communication bandwidth demands of HPC-systems calling at the same time for reduced latency and increased power efficiency have designated optical interconnects as the key technology in order to achieve the target of exascale performance. ...
PhoenixSim: Crosslayer Design and Modeling of Silicon Photonic Interconnects
Silicon Photonics is emerging as a key technology for high-performance computing interconnects. Yet few tools are available to investigate how to best leverage this technology in current or future computer architectures and, furthermore, how this ...
JADE: a Heterogeneous Multiprocessor System Simulation Platform Using Recorded and Statistical Application Models
- Rafael K. V. Maeda,
- Peng Yang,
- Xiaowen Wu,
- Zhe Wang,
- Jiang Xu,
- Zhehui Wang,
- Haoran Li,
- Luan H. K. Duong,
- Zhifei Wang
Recent advances in the computing industry towards multiprocessor technologies shifted the dominant method of performance increase from frequency scaling to parallelism. Due to its huge design space, evaluating candidate multicore architectures in early ...
Index Terms
- Proceedings of the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems
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Acceptance Rates
| Year | Submitted | Accepted | Rate |
|---|---|---|---|
| AISTECS '17 | 8 | 7 | 88% |
| Overall | 8 | 7 | 88% |