research-article

Shared Last-Level Caches and The Case for Longer Timeslices

Authors:

Viacheslav V. Fedorov,

A. L. Narasimha Reddy,

Paul V. GratzAuthors Info & Claims

MEMSYS '15: Proceedings of the 2015 International Symposium on Memory Systems

Pages 113 - 120

https://doi.org/10.1145/2818950.2818968

Published: 05 October 2015 Publication History

Abstract

Memory performance is important in modern systems. Contention at various levels in memory hierarchy can lead to significant application performance degradation due to interference. Further, modern, large, last-level caches (LLC) have fill times greater than the OS scheduling window. When several threads are running concurrently and timesharing the CPU cores, they may never be able to load their working sets into the cache before being rescheduled, thus permanently stuck in the "cold-start" regime. We show that by increasing the system scheduling timeslice length it is possible to amortize the cache cold-start penalty due to the multitasking and improve application performance by 10--15%.

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Cited By

Jose JBegum SRamasubrmanian N. (2022)Effectiveness Evaluation of Replacement Policies for On-Chip Caches in MultiprocessorsInternational Journal of Embedded and Real-Time Communication Systems10.4018/IJERTCS.28920213:1(1-12)Online publication date: 14-Jan-2022
https://dl.acm.org/doi/10.4018/IJERTCS.289202
Kotra JShahidi NChishti ZKandemir M(2017)Hardware-Software Co-design to Mitigate DRAM Refresh OverheadsACM SIGARCH Computer Architecture News10.1145/3093337.303772445:1(723-736)Online publication date: 4-Apr-2017
https://dl.acm.org/doi/10.1145/3093337.3037724
Kotra JShahidi NChishti ZKandemir M(2017)Hardware-Software Co-design to Mitigate DRAM Refresh OverheadsACM SIGPLAN Notices10.1145/3093336.303772452:4(723-736)Online publication date: 4-Apr-2017
https://dl.acm.org/doi/10.1145/3093336.3037724
Show More Cited By

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Shared Last-Level Caches and The Case for Longer Timeslices

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cover image ACM Other conferences

MEMSYS '15: Proceedings of the 2015 International Symposium on Memory Systems

October 2015

278 pages

ISBN:9781450336048

DOI:10.1145/2818950

Copyright © 2015 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 05 October 2015

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MEMSYS '15

MEMSYS '15: International Symposium on Memory Systems

October 5 - 8, 2015

DC, Washington DC, USA

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Cited By

Jose JBegum SRamasubrmanian N. (2022)Effectiveness Evaluation of Replacement Policies for On-Chip Caches in MultiprocessorsInternational Journal of Embedded and Real-Time Communication Systems10.4018/IJERTCS.28920213:1(1-12)Online publication date: 14-Jan-2022
https://dl.acm.org/doi/10.4018/IJERTCS.289202
Kotra JShahidi NChishti ZKandemir M(2017)Hardware-Software Co-design to Mitigate DRAM Refresh OverheadsACM SIGARCH Computer Architecture News10.1145/3093337.303772445:1(723-736)Online publication date: 4-Apr-2017
https://dl.acm.org/doi/10.1145/3093337.3037724
Kotra JShahidi NChishti ZKandemir M(2017)Hardware-Software Co-design to Mitigate DRAM Refresh OverheadsACM SIGPLAN Notices10.1145/3093336.303772452:4(723-736)Online publication date: 4-Apr-2017
https://dl.acm.org/doi/10.1145/3093336.3037724
Kotra JShahidi NChishti ZKandemir M(2017)Hardware-Software Co-design to Mitigate DRAM Refresh OverheadsACM SIGOPS Operating Systems Review10.1145/3093315.303772451:2(723-736)Online publication date: 4-Apr-2017
https://doi.org/10.1145/3093315.3037724
Kotra JShahidi NChishti ZKandemir MChen YTemam OCarter J(2017)Hardware-Software Co-design to Mitigate DRAM Refresh OverheadsProceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3037697.3037724(723-736)Online publication date: 4-Apr-2017
https://dl.acm.org/doi/10.1145/3037697.3037724

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